Skip to content

Commit fddcb0d

Browse files
farzonlfarzonl
committed
run clang format
1 parent b1d3357 commit fddcb0d

File tree

6 files changed

+33
-36
lines changed

6 files changed

+33
-36
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4425,9 +4425,8 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
44254425
break;
44264426
case ISD::FTAN:
44274427
case ISD::STRICT_FTAN:
4428-
ExpandFPLibCall(Node, RTLIB::TAN_F32, RTLIB::TAN_F64,
4429-
RTLIB::TAN_F80, RTLIB::TAN_F128,
4430-
RTLIB::TAN_PPCF128, Results);
4428+
ExpandFPLibCall(Node, RTLIB::TAN_F32, RTLIB::TAN_F64, RTLIB::TAN_F80,
4429+
RTLIB::TAN_F128, RTLIB::TAN_PPCF128, Results);
44314430
break;
44324431
case ISD::FSINCOS:
44334432
// Expand into sincos libcall.

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -776,12 +776,9 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
776776
}
777777

778778
SDValue DAGTypeLegalizer::SoftenFloatRes_FTAN(SDNode *N) {
779-
return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
780-
RTLIB::TAN_F32,
781-
RTLIB::TAN_F64,
782-
RTLIB::TAN_F80,
783-
RTLIB::TAN_F128,
784-
RTLIB::TAN_PPCF128));
779+
return SoftenFloatRes_Unary(
780+
N, GetFPLibCall(N->getValueType(0), RTLIB::TAN_F32, RTLIB::TAN_F64,
781+
RTLIB::TAN_F80, RTLIB::TAN_F128, RTLIB::TAN_PPCF128));
785782
}
786783

787784
SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) {
@@ -1373,7 +1370,9 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
13731370
case ISD::STRICT_FSUB:
13741371
case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
13751372
case ISD::STRICT_FTAN:
1376-
case ISD::FTAN: ExpandFloatRes_FTAN(N, Lo, Hi); break;
1373+
case ISD::FTAN:
1374+
ExpandFloatRes_FTAN(N, Lo, Hi);
1375+
break;
13771376
case ISD::STRICT_FTRUNC:
13781377
case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break;
13791378
case ISD::LOAD: ExpandFloatRes_LOAD(N, Lo, Hi); break;
@@ -1743,12 +1742,13 @@ void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo,
17431742
RTLIB::SUB_PPCF128), Lo, Hi);
17441743
}
17451744

1746-
void DAGTypeLegalizer::ExpandFloatRes_FTAN(SDNode *N,
1747-
SDValue &Lo, SDValue &Hi) {
1748-
ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1749-
RTLIB::TAN_F32, RTLIB::TAN_F64,
1750-
RTLIB::TAN_F80, RTLIB::TAN_F128,
1751-
RTLIB::TAN_PPCF128), Lo, Hi);
1745+
void DAGTypeLegalizer::ExpandFloatRes_FTAN(SDNode *N, SDValue &Lo,
1746+
SDValue &Hi) {
1747+
ExpandFloatRes_Unary(N,
1748+
GetFPLibCall(N->getValueType(0), RTLIB::TAN_F32,
1749+
RTLIB::TAN_F64, RTLIB::TAN_F80,
1750+
RTLIB::TAN_F128, RTLIB::TAN_PPCF128),
1751+
Lo, Hi);
17521752
}
17531753

17541754
void DAGTypeLegalizer::ExpandFloatRes_FTRUNC(SDNode *N,

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -646,7 +646,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
646646
void ExpandFloatRes_FSIN (SDNode *N, SDValue &Lo, SDValue &Hi);
647647
void ExpandFloatRes_FSQRT (SDNode *N, SDValue &Lo, SDValue &Hi);
648648
void ExpandFloatRes_FSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
649-
void ExpandFloatRes_FTAN (SDNode *N, SDValue &Lo, SDValue &Hi);
649+
void ExpandFloatRes_FTAN(SDNode *N, SDValue &Lo, SDValue &Hi);
650650
void ExpandFloatRes_FTRUNC (SDNode *N, SDValue &Lo, SDValue &Hi);
651651
void ExpandFloatRes_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
652652
void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6707,7 +6707,9 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
67076707
case Intrinsic::fabs: Opcode = ISD::FABS; break;
67086708
case Intrinsic::sin: Opcode = ISD::FSIN; break;
67096709
case Intrinsic::cos: Opcode = ISD::FCOS; break;
6710-
case Intrinsic::tan: Opcode = ISD::FTAN; break;
6710+
case Intrinsic::tan:
6711+
Opcode = ISD::FTAN;
6712+
break;
67116713
case Intrinsic::exp10: Opcode = ISD::FEXP10; break;
67126714
case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
67136715
case Intrinsic::ceil: Opcode = ISD::FCEIL; break;

‎llvm/lib/CodeGen/TargetLoweringBase.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -988,7 +988,8 @@ void TargetLoweringBase::initActions() {
988988
setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP,
989989
ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR, ISD::FNEARBYINT,
990990
ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, ISD::LROUND,
991-
ISD::LLROUND, ISD::LRINT, ISD::LLRINT, ISD::FROUNDEVEN, ISD::FTAN},
991+
ISD::LLROUND, ISD::LRINT, ISD::LLRINT, ISD::FROUNDEVEN,
992+
ISD::FTAN},
992993
{MVT::f32, MVT::f64, MVT::f128}, Expand);
993994

994995
// Default ISD::TRAP to expand (which turns it into abort).

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 12 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -655,7 +655,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
655655
setOperationAction(ISD::FSIN , VT, Expand);
656656
setOperationAction(ISD::FCOS , VT, Expand);
657657
setOperationAction(ISD::FSINCOS, VT, Expand);
658-
setOperationAction(ISD::FTAN , VT, Expand);
658+
setOperationAction(ISD::FTAN, VT, Expand);
659659
}
660660

661661
// Half type will be promoted by default.
@@ -731,7 +731,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
731731
setOperationAction(ISD::FSIN , MVT::f32, Expand);
732732
setOperationAction(ISD::FCOS , MVT::f32, Expand);
733733
setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
734-
setOperationAction(ISD::FTAN , MVT::f32, Expand);
734+
setOperationAction(ISD::FTAN, MVT::f32, Expand);
735735

736736
if (UseX87) {
737737
// Always expand sin/cos functions even though x87 has an instruction.
@@ -754,7 +754,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
754754
setOperationAction(ISD::FSIN , VT, Expand);
755755
setOperationAction(ISD::FCOS , VT, Expand);
756756
setOperationAction(ISD::FSINCOS, VT, Expand);
757-
setOperationAction(ISD::FTAN , VT, Expand);
757+
setOperationAction(ISD::FTAN, VT, Expand);
758758
}
759759
}
760760

@@ -824,7 +824,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
824824
setOperationAction(ISD::FSIN , MVT::f80, Expand);
825825
setOperationAction(ISD::FCOS , MVT::f80, Expand);
826826
setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
827-
setOperationAction(ISD::FTAN , MVT::f80, Expand);
827+
setOperationAction(ISD::FTAN, MVT::f80, Expand);
828828

829829
setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
830830
setOperationAction(ISD::FCEIL, MVT::f80, Expand);
@@ -882,8 +882,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
882882
setOperationAction(ISD::FCOS, MVT::f128, LibCall);
883883
setOperationAction(ISD::STRICT_FCOS, MVT::f128, LibCall);
884884
setOperationAction(ISD::FSINCOS, MVT::f128, LibCall);
885-
setOperationAction(ISD::FTAN, MVT::f128, LibCall);
886-
setOperationAction(ISD::STRICT_FTAN, MVT::f128, LibCall);
885+
setOperationAction(ISD::FTAN, MVT::f128, LibCall);
886+
setOperationAction(ISD::STRICT_FTAN, MVT::f128, LibCall);
887887
// No STRICT_FSINCOS
888888
setOperationAction(ISD::FSQRT, MVT::f128, LibCall);
889889
setOperationAction(ISD::STRICT_FSQRT, MVT::f128, LibCall);
@@ -938,7 +938,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
938938
setOperationAction(ISD::FSIN, VT, Expand);
939939
setOperationAction(ISD::FSINCOS, VT, Expand);
940940
setOperationAction(ISD::FCOS, VT, Expand);
941-
setOperationAction(ISD::FTAN, VT, Expand);
941+
setOperationAction(ISD::FTAN, VT, Expand);
942942
setOperationAction(ISD::FREM, VT, Expand);
943943
setOperationAction(ISD::FCOPYSIGN, VT, Expand);
944944
setOperationAction(ISD::FPOW, VT, Expand);
@@ -2458,16 +2458,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
24582458
if (Subtarget.is32Bit() &&
24592459
(Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()))
24602460
for (ISD::NodeType Op :
2461-
{ISD::FCEIL, ISD::STRICT_FCEIL,
2462-
ISD::FCOS, ISD::STRICT_FCOS,
2463-
ISD::FEXP, ISD::STRICT_FEXP,
2464-
ISD::FFLOOR, ISD::STRICT_FFLOOR,
2465-
ISD::FREM, ISD::STRICT_FREM,
2466-
ISD::FLOG, ISD::STRICT_FLOG,
2467-
ISD::FLOG10, ISD::STRICT_FLOG10,
2468-
ISD::FPOW, ISD::STRICT_FPOW,
2469-
ISD::FSIN, ISD::STRICT_FSIN,
2470-
ISD::FTAN, ISD::STRICT_FTAN})
2461+
{ISD::FCEIL, ISD::STRICT_FCEIL, ISD::FCOS, ISD::STRICT_FCOS,
2462+
ISD::FEXP, ISD::STRICT_FEXP, ISD::FFLOOR, ISD::STRICT_FFLOOR,
2463+
ISD::FREM, ISD::STRICT_FREM, ISD::FLOG, ISD::STRICT_FLOG,
2464+
ISD::FLOG10, ISD::STRICT_FLOG10, ISD::FPOW, ISD::STRICT_FPOW,
2465+
ISD::FSIN, ISD::STRICT_FSIN, ISD::FTAN, ISD::STRICT_FTAN})
24712466
if (isOperationExpand(Op, MVT::f32))
24722467
setOperationAction(Op, MVT::f32, Promote);
24732468

0 commit comments

Comments
 (0)