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davemgreendavemgreen
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[AArch64] Add patterns for add(uzp1(x,y), uzp2(x, y)) -> addp.
If we are extracting the even lanes and the odd lanes and adding them, we can use an addp instruction.
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5 files changed

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-113
lines changed

5 files changed

+102
-113
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9405,6 +9405,20 @@ def : Pat<(AArch64faddp (v4f16 (extract_subvector (v8f16 FPR128:$Rn), (i64 0))),
94059405
(v4f16 (extract_subvector (v8f16 FPR128:$Rn), (i64 4)))),
94069406
(v4f16 (EXTRACT_SUBREG (FADDPv8f16 $Rn, $Rn), dsub))>;
94079407

9408+
// add(uzp1(X, Y), uzp2(X, Y)) -> addp(X, Y)
9409+
def : Pat<(v2i64 (add (AArch64zip1 (v2i64 FPR128:$Rn), (v2i64 FPR128:$Rm)),
9410+
(AArch64zip2 (v2i64 FPR128:$Rn), (v2i64 FPR128:$Rm)))),
9411+
(v2i64 (ADDPv2i64 $Rn, $Rm))>;
9412+
def : Pat<(v4i32 (add (AArch64uzp1 (v4i32 FPR128:$Rn), (v4i32 FPR128:$Rm)),
9413+
(AArch64uzp2 (v4i32 FPR128:$Rn), (v4i32 FPR128:$Rm)))),
9414+
(v4i32 (ADDPv4i32 $Rn, $Rm))>;
9415+
def : Pat<(v8i16 (add (AArch64uzp1 (v8i16 FPR128:$Rn), (v8i16 FPR128:$Rm)),
9416+
(AArch64uzp2 (v8i16 FPR128:$Rn), (v8i16 FPR128:$Rm)))),
9417+
(v8i16 (ADDPv8i16 $Rn, $Rm))>;
9418+
def : Pat<(v16i8 (add (AArch64uzp1 (v16i8 FPR128:$Rn), (v16i8 FPR128:$Rm)),
9419+
(AArch64uzp2 (v16i8 FPR128:$Rn), (v16i8 FPR128:$Rm)))),
9420+
(v16i8 (ADDPv16i8 $Rn, $Rm))>;
9421+
94089422
// Scalar 64-bit shifts in FPR64 registers.
94099423
def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
94109424
(SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;

‎llvm/test/CodeGen/AArch64/addp-shuffle.ll

Lines changed: 13 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,7 @@
55
define <4 x i32> @deinterleave_shuffle_v8i32(<8 x i32> %a) {
66
; CHECK-LABEL: deinterleave_shuffle_v8i32:
77
; CHECK: // %bb.0:
8-
; CHECK-NEXT: uzp1 v2.4s, v0.4s, v1.4s
9-
; CHECK-NEXT: uzp2 v0.4s, v0.4s, v1.4s
10-
; CHECK-NEXT: add v0.4s, v2.4s, v0.4s
8+
; CHECK-NEXT: addp v0.4s, v0.4s, v1.4s
119
; CHECK-NEXT: ret
1210
%r0 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
1311
%r1 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
@@ -18,9 +16,7 @@ define <4 x i32> @deinterleave_shuffle_v8i32(<8 x i32> %a) {
1816
define <4 x i32> @deinterleave_shuffle_v8i32_c(<8 x i32> %a) {
1917
; CHECK-LABEL: deinterleave_shuffle_v8i32_c:
2018
; CHECK: // %bb.0:
21-
; CHECK-NEXT: uzp1 v2.4s, v0.4s, v1.4s
22-
; CHECK-NEXT: uzp2 v0.4s, v0.4s, v1.4s
23-
; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
19+
; CHECK-NEXT: addp v0.4s, v0.4s, v1.4s
2420
; CHECK-NEXT: ret
2521
%r0 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
2622
%r1 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
@@ -45,9 +41,7 @@ define <2 x i32> @deinterleave_shuffle_v4i32(<4 x i32> %a) {
4541
define <8 x i16> @deinterleave_shuffle_v16i16(<16 x i16> %a) {
4642
; CHECK-LABEL: deinterleave_shuffle_v16i16:
4743
; CHECK: // %bb.0:
48-
; CHECK-NEXT: uzp1 v2.8h, v0.8h, v1.8h
49-
; CHECK-NEXT: uzp2 v0.8h, v0.8h, v1.8h
50-
; CHECK-NEXT: add v0.8h, v2.8h, v0.8h
44+
; CHECK-NEXT: addp v0.8h, v0.8h, v1.8h
5145
; CHECK-NEXT: ret
5246
%r0 = shufflevector <16 x i16> %a, <16 x i16> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
5347
%r1 = shufflevector <16 x i16> %a, <16 x i16> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
@@ -58,9 +52,7 @@ define <8 x i16> @deinterleave_shuffle_v16i16(<16 x i16> %a) {
5852
define <16 x i8> @deinterleave_shuffle_v32i8(<32 x i8> %a) {
5953
; CHECK-LABEL: deinterleave_shuffle_v32i8:
6054
; CHECK: // %bb.0:
61-
; CHECK-NEXT: uzp1 v2.16b, v0.16b, v1.16b
62-
; CHECK-NEXT: uzp2 v0.16b, v0.16b, v1.16b
63-
; CHECK-NEXT: add v0.16b, v2.16b, v0.16b
55+
; CHECK-NEXT: addp v0.16b, v0.16b, v1.16b
6456
; CHECK-NEXT: ret
6557
%r0 = shufflevector <32 x i8> %a, <32 x i8> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
6658
%r1 = shufflevector <32 x i8> %a, <32 x i8> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
@@ -71,12 +63,9 @@ define <16 x i8> @deinterleave_shuffle_v32i8(<32 x i8> %a) {
7163
define <4 x i64> @deinterleave_shuffle_v8i64(<8 x i64> %a) {
7264
; CHECK-LABEL: deinterleave_shuffle_v8i64:
7365
; CHECK: // %bb.0:
74-
; CHECK-NEXT: zip1 v4.2d, v2.2d, v3.2d
75-
; CHECK-NEXT: zip1 v5.2d, v0.2d, v1.2d
76-
; CHECK-NEXT: zip2 v2.2d, v2.2d, v3.2d
77-
; CHECK-NEXT: zip2 v0.2d, v0.2d, v1.2d
78-
; CHECK-NEXT: add v1.2d, v4.2d, v2.2d
79-
; CHECK-NEXT: add v0.2d, v5.2d, v0.2d
66+
; CHECK-NEXT: addp v2.2d, v2.2d, v3.2d
67+
; CHECK-NEXT: addp v0.2d, v0.2d, v1.2d
68+
; CHECK-NEXT: mov v1.16b, v2.16b
8069
; CHECK-NEXT: ret
8170
%r0 = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
8271
%r1 = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
@@ -164,15 +153,9 @@ define <4 x i32> @udot(<4 x i32> %z, <16 x i8> %a, <16 x i8> %b) {
164153
; CHECK-NEXT: umull v3.4s, v3.4h, v4.4h
165154
; CHECK-NEXT: umull2 v4.4s, v1.8h, v2.8h
166155
; CHECK-NEXT: umull v1.4s, v1.4h, v2.4h
167-
; CHECK-NEXT: uzp1 v2.4s, v3.4s, v5.4s
168-
; CHECK-NEXT: uzp2 v3.4s, v3.4s, v5.4s
169-
; CHECK-NEXT: uzp1 v6.4s, v1.4s, v4.4s
170-
; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
171-
; CHECK-NEXT: add v2.4s, v2.4s, v3.4s
172-
; CHECK-NEXT: add v1.4s, v6.4s, v1.4s
173-
; CHECK-NEXT: uzp1 v3.4s, v2.4s, v1.4s
174-
; CHECK-NEXT: uzp2 v1.4s, v2.4s, v1.4s
175-
; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
156+
; CHECK-NEXT: addp v2.4s, v3.4s, v5.4s
157+
; CHECK-NEXT: addp v1.4s, v1.4s, v4.4s
158+
; CHECK-NEXT: addp v1.4s, v2.4s, v1.4s
176159
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
177160
; CHECK-NEXT: ret
178161
%za = zext <16 x i8> %a to <16 x i32>
@@ -199,15 +182,9 @@ define <4 x i32> @sdot(<4 x i32> %z, <16 x i8> %a, <16 x i8> %b) {
199182
; CHECK-NEXT: smull v3.4s, v3.4h, v4.4h
200183
; CHECK-NEXT: smull2 v4.4s, v1.8h, v2.8h
201184
; CHECK-NEXT: smull v1.4s, v1.4h, v2.4h
202-
; CHECK-NEXT: uzp1 v2.4s, v3.4s, v5.4s
203-
; CHECK-NEXT: uzp2 v3.4s, v3.4s, v5.4s
204-
; CHECK-NEXT: uzp1 v6.4s, v1.4s, v4.4s
205-
; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
206-
; CHECK-NEXT: add v2.4s, v2.4s, v3.4s
207-
; CHECK-NEXT: add v1.4s, v6.4s, v1.4s
208-
; CHECK-NEXT: uzp1 v3.4s, v2.4s, v1.4s
209-
; CHECK-NEXT: uzp2 v1.4s, v2.4s, v1.4s
210-
; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
185+
; CHECK-NEXT: addp v2.4s, v3.4s, v5.4s
186+
; CHECK-NEXT: addp v1.4s, v1.4s, v4.4s
187+
; CHECK-NEXT: addp v1.4s, v2.4s, v1.4s
211188
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
212189
; CHECK-NEXT: ret
213190
%za = sext <16 x i8> %a to <16 x i32>

‎llvm/test/CodeGen/AArch64/arm64-uzp.ll

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -33,11 +33,11 @@ define <16 x i8> @vuzpQi8(<16 x i8> %A, <16 x i8> %B) nounwind {
3333
; CHECK: // %bb.0:
3434
; CHECK-NEXT: uzp1.16b v2, v0, v1
3535
; CHECK-NEXT: uzp2.16b v0, v0, v1
36-
; CHECK-NEXT: add.16b v0, v2, v0
36+
; CHECK-NEXT: eor.16b v0, v2, v0
3737
; CHECK-NEXT: ret
3838
%tmp3 = shufflevector <16 x i8> %A, <16 x i8> %B, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
3939
%tmp4 = shufflevector <16 x i8> %A, <16 x i8> %B, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
40-
%tmp5 = add <16 x i8> %tmp3, %tmp4
40+
%tmp5 = xor <16 x i8> %tmp3, %tmp4
4141
ret <16 x i8> %tmp5
4242
}
4343

@@ -46,11 +46,11 @@ define <8 x i16> @vuzpQi16(<8 x i16> %A, <8 x i16> %B) nounwind {
4646
; CHECK: // %bb.0:
4747
; CHECK-NEXT: uzp1.8h v2, v0, v1
4848
; CHECK-NEXT: uzp2.8h v0, v0, v1
49-
; CHECK-NEXT: add.8h v0, v2, v0
49+
; CHECK-NEXT: eor.16b v0, v2, v0
5050
; CHECK-NEXT: ret
5151
%tmp3 = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
5252
%tmp4 = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
53-
%tmp5 = add <8 x i16> %tmp3, %tmp4
53+
%tmp5 = xor <8 x i16> %tmp3, %tmp4
5454
ret <8 x i16> %tmp5
5555
}
5656

@@ -59,11 +59,11 @@ define <4 x i32> @vuzpQi32(<4 x i32> %A, <4 x i32> %B) nounwind {
5959
; CHECK: // %bb.0:
6060
; CHECK-NEXT: uzp1.4s v2, v0, v1
6161
; CHECK-NEXT: uzp2.4s v0, v0, v1
62-
; CHECK-NEXT: add.4s v0, v2, v0
62+
; CHECK-NEXT: eor.16b v0, v2, v0
6363
; CHECK-NEXT: ret
6464
%tmp3 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
6565
%tmp4 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
66-
%tmp5 = add <4 x i32> %tmp3, %tmp4
66+
%tmp5 = xor <4 x i32> %tmp3, %tmp4
6767
ret <4 x i32> %tmp5
6868
}
6969

@@ -72,11 +72,11 @@ define <4 x float> @vuzpQf(<4 x float> %A, <4 x float> %B) nounwind {
7272
; CHECK: // %bb.0:
7373
; CHECK-NEXT: uzp1.4s v2, v0, v1
7474
; CHECK-NEXT: uzp2.4s v0, v0, v1
75-
; CHECK-NEXT: fadd.4s v0, v2, v0
75+
; CHECK-NEXT: fsub.4s v0, v2, v0
7676
; CHECK-NEXT: ret
7777
%tmp3 = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
7878
%tmp4 = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
79-
%tmp5 = fadd <4 x float> %tmp3, %tmp4
79+
%tmp5 = fsub <4 x float> %tmp3, %tmp4
8080
ret <4 x float> %tmp5
8181
}
8282

@@ -100,11 +100,11 @@ define <8 x i16> @vuzpQi16_undef1(<8 x i16> %A, <8 x i16> %B) nounwind {
100100
; CHECK: // %bb.0:
101101
; CHECK-NEXT: uzp1.8h v2, v0, v1
102102
; CHECK-NEXT: uzp2.8h v0, v0, v1
103-
; CHECK-NEXT: add.8h v0, v2, v0
103+
; CHECK-NEXT: eor.16b v0, v2, v0
104104
; CHECK-NEXT: ret
105105
%tmp3 = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14>
106106
%tmp4 = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
107-
%tmp5 = add <8 x i16> %tmp3, %tmp4
107+
%tmp5 = xor <8 x i16> %tmp3, %tmp4
108108
ret <8 x i16> %tmp5
109109
}
110110

@@ -113,11 +113,11 @@ define <8 x i16> @vuzpQi16_undef0(<8 x i16> %A, <8 x i16> %B) nounwind {
113113
; CHECK: // %bb.0:
114114
; CHECK-NEXT: uzp1.8h v2, v0, v1
115115
; CHECK-NEXT: uzp2.8h v0, v0, v1
116-
; CHECK-NEXT: add.8h v0, v2, v0
116+
; CHECK-NEXT: eor.16b v0, v2, v0
117117
; CHECK-NEXT: ret
118118
%tmp3 = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 undef, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
119119
%tmp4 = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 undef, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
120-
%tmp5 = add <8 x i16> %tmp3, %tmp4
120+
%tmp5 = xor <8 x i16> %tmp3, %tmp4
121121
ret <8 x i16> %tmp5
122122
}
123123

@@ -126,11 +126,11 @@ define <8 x i16> @vuzpQi16_undef01(<8 x i16> %A, <8 x i16> %B) nounwind {
126126
; CHECK: // %bb.0:
127127
; CHECK-NEXT: uzp1.8h v2, v0, v1
128128
; CHECK-NEXT: uzp2.8h v0, v0, v1
129-
; CHECK-NEXT: add.8h v0, v2, v0
129+
; CHECK-NEXT: eor.16b v0, v2, v0
130130
; CHECK-NEXT: ret
131131
%tmp3 = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 undef, i32 undef, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
132132
%tmp4 = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 undef, i32 undef, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
133-
%tmp5 = add <8 x i16> %tmp3, %tmp4
133+
%tmp5 = xor <8 x i16> %tmp3, %tmp4
134134
ret <8 x i16> %tmp5
135135
}
136136

@@ -139,10 +139,10 @@ define <8 x i16> @vuzpQi16_undef012(<8 x i16> %A, <8 x i16> %B) nounwind {
139139
; CHECK: // %bb.0:
140140
; CHECK-NEXT: uzp1.8h v2, v0, v1
141141
; CHECK-NEXT: uzp2.8h v0, v0, v1
142-
; CHECK-NEXT: add.8h v0, v2, v0
142+
; CHECK-NEXT: eor.16b v0, v2, v0
143143
; CHECK-NEXT: ret
144144
%tmp3 = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 6, i32 8, i32 10, i32 12, i32 14>
145145
%tmp4 = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 7, i32 9, i32 11, i32 13, i32 15>
146-
%tmp5 = add <8 x i16> %tmp3, %tmp4
146+
%tmp5 = xor <8 x i16> %tmp3, %tmp4
147147
ret <8 x i16> %tmp5
148148
}

‎llvm/test/CodeGen/AArch64/insert-extend.ll

Lines changed: 57 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -94,75 +94,73 @@ define i32 @large(ptr nocapture noundef readonly %p1, i32 noundef %st1, ptr noca
9494
; CHECK-NEXT: mov v3.d[1], v5.d[1]
9595
; CHECK-NEXT: uzp1 v1.4s, v4.4s, v0.4s
9696
; CHECK-NEXT: uzp2 v4.4s, v4.4s, v0.4s
97-
; CHECK-NEXT: uzp2 v5.4s, v2.4s, v0.4s
98-
; CHECK-NEXT: uzp1 v0.4s, v2.4s, v0.4s
99-
; CHECK-NEXT: add v2.4s, v3.4s, v6.4s
97+
; CHECK-NEXT: addp v0.4s, v2.4s, v0.4s
98+
; CHECK-NEXT: add v5.4s, v3.4s, v6.4s
10099
; CHECK-NEXT: sub v3.4s, v6.4s, v3.4s
101-
; CHECK-NEXT: sub v1.4s, v1.4s, v4.4s
102-
; CHECK-NEXT: add v0.4s, v5.4s, v0.4s
103-
; CHECK-NEXT: rev64 v4.4s, v2.4s
104-
; CHECK-NEXT: rev64 v5.4s, v3.4s
105-
; CHECK-NEXT: rev64 v6.4s, v1.4s
106100
; CHECK-NEXT: rev64 v7.4s, v0.4s
107-
; CHECK-NEXT: addp v16.4s, v1.4s, v3.4s
108-
; CHECK-NEXT: addp v17.4s, v0.4s, v2.4s
109-
; CHECK-NEXT: sub v3.4s, v3.4s, v5.4s
110-
; CHECK-NEXT: sub v2.4s, v2.4s, v4.4s
111-
; CHECK-NEXT: sub v1.4s, v1.4s, v6.4s
101+
; CHECK-NEXT: sub v1.4s, v1.4s, v4.4s
102+
; CHECK-NEXT: rev64 v4.4s, v5.4s
103+
; CHECK-NEXT: rev64 v6.4s, v3.4s
104+
; CHECK-NEXT: addp v16.4s, v0.4s, v5.4s
105+
; CHECK-NEXT: rev64 v2.4s, v1.4s
112106
; CHECK-NEXT: sub v0.4s, v0.4s, v7.4s
113-
; CHECK-NEXT: zip1 v18.4s, v17.4s, v17.4s
114-
; CHECK-NEXT: ext v4.16b, v17.16b, v2.16b, #4
115-
; CHECK-NEXT: ext v5.16b, v16.16b, v3.16b, #4
107+
; CHECK-NEXT: zip1 v21.4s, v16.4s, v16.4s
108+
; CHECK-NEXT: sub v4.4s, v5.4s, v4.4s
109+
; CHECK-NEXT: addp v5.4s, v1.4s, v3.4s
110+
; CHECK-NEXT: sub v3.4s, v3.4s, v6.4s
111+
; CHECK-NEXT: sub v1.4s, v1.4s, v2.4s
112+
; CHECK-NEXT: ext v7.16b, v0.16b, v16.16b, #4
113+
; CHECK-NEXT: ext v2.16b, v16.16b, v4.16b, #4
114+
; CHECK-NEXT: ext v6.16b, v5.16b, v3.16b, #4
115+
; CHECK-NEXT: mov v19.16b, v4.16b
116+
; CHECK-NEXT: ext v17.16b, v1.16b, v5.16b, #8
116117
; CHECK-NEXT: mov v20.16b, v3.16b
117-
; CHECK-NEXT: ext v6.16b, v1.16b, v16.16b, #8
118-
; CHECK-NEXT: ext v7.16b, v0.16b, v17.16b, #4
119-
; CHECK-NEXT: mov v21.16b, v2.16b
120-
; CHECK-NEXT: trn2 v0.4s, v18.4s, v0.4s
121-
; CHECK-NEXT: mov v20.s[2], v16.s[3]
122-
; CHECK-NEXT: zip2 v4.4s, v4.4s, v17.4s
123-
; CHECK-NEXT: zip2 v5.4s, v5.4s, v16.4s
124-
; CHECK-NEXT: mov v21.s[2], v17.s[3]
125-
; CHECK-NEXT: ext v19.16b, v6.16b, v1.16b, #4
118+
; CHECK-NEXT: trn2 v0.4s, v21.4s, v0.4s
126119
; CHECK-NEXT: ext v7.16b, v7.16b, v7.16b, #4
127-
; CHECK-NEXT: mov v1.s[2], v16.s[1]
128-
; CHECK-NEXT: ext v2.16b, v2.16b, v4.16b, #12
129-
; CHECK-NEXT: ext v3.16b, v3.16b, v5.16b, #12
130-
; CHECK-NEXT: uzp2 v4.4s, v6.4s, v19.4s
131-
; CHECK-NEXT: mov v5.16b, v7.16b
132-
; CHECK-NEXT: mov v6.16b, v20.16b
133-
; CHECK-NEXT: mov v18.16b, v1.16b
134-
; CHECK-NEXT: mov v19.16b, v21.16b
120+
; CHECK-NEXT: mov v19.s[2], v16.s[3]
121+
; CHECK-NEXT: zip2 v2.4s, v2.4s, v16.4s
122+
; CHECK-NEXT: zip2 v6.4s, v6.4s, v5.4s
123+
; CHECK-NEXT: mov v20.s[2], v5.s[3]
124+
; CHECK-NEXT: ext v18.16b, v17.16b, v1.16b, #4
125+
; CHECK-NEXT: mov v1.s[2], v5.s[1]
126+
; CHECK-NEXT: mov v21.16b, v7.16b
135127
; CHECK-NEXT: sub v7.4s, v0.4s, v7.4s
136-
; CHECK-NEXT: mov v6.s[1], v16.s[2]
137-
; CHECK-NEXT: mov v5.s[0], v17.s[1]
138-
; CHECK-NEXT: mov v18.s[1], v16.s[0]
139-
; CHECK-NEXT: mov v19.s[1], v17.s[2]
128+
; CHECK-NEXT: ext v2.16b, v4.16b, v2.16b, #12
129+
; CHECK-NEXT: ext v3.16b, v3.16b, v6.16b, #12
130+
; CHECK-NEXT: uzp2 v4.4s, v17.4s, v18.4s
131+
; CHECK-NEXT: mov v6.16b, v1.16b
132+
; CHECK-NEXT: mov v17.16b, v19.16b
133+
; CHECK-NEXT: mov v18.16b, v20.16b
134+
; CHECK-NEXT: mov v21.s[0], v16.s[1]
135+
; CHECK-NEXT: mov v6.s[1], v5.s[0]
136+
; CHECK-NEXT: mov v17.s[1], v16.s[2]
137+
; CHECK-NEXT: sub v16.4s, v19.4s, v2.4s
138+
; CHECK-NEXT: mov v18.s[1], v5.s[2]
140139
; CHECK-NEXT: sub v1.4s, v1.4s, v4.4s
141-
; CHECK-NEXT: sub v16.4s, v20.4s, v3.4s
142-
; CHECK-NEXT: sub v17.4s, v21.4s, v2.4s
143-
; CHECK-NEXT: add v3.4s, v6.4s, v3.4s
144-
; CHECK-NEXT: add v0.4s, v0.4s, v5.4s
145-
; CHECK-NEXT: add v4.4s, v18.4s, v4.4s
146-
; CHECK-NEXT: add v2.4s, v19.4s, v2.4s
147-
; CHECK-NEXT: mov v3.d[1], v16.d[1]
140+
; CHECK-NEXT: sub v5.4s, v20.4s, v3.4s
141+
; CHECK-NEXT: add v0.4s, v0.4s, v21.4s
142+
; CHECK-NEXT: add v4.4s, v6.4s, v4.4s
143+
; CHECK-NEXT: add v2.4s, v17.4s, v2.4s
144+
; CHECK-NEXT: add v3.4s, v18.4s, v3.4s
148145
; CHECK-NEXT: mov v0.d[1], v7.d[1]
149146
; CHECK-NEXT: mov v4.d[1], v1.d[1]
150-
; CHECK-NEXT: mov v2.d[1], v17.d[1]
151-
; CHECK-NEXT: cmlt v1.8h, v3.8h, #0
152-
; CHECK-NEXT: cmlt v5.8h, v0.8h, #0
153-
; CHECK-NEXT: cmlt v6.8h, v4.8h, #0
154-
; CHECK-NEXT: cmlt v7.8h, v2.8h, #0
155-
; CHECK-NEXT: add v3.4s, v1.4s, v3.4s
156-
; CHECK-NEXT: add v0.4s, v5.4s, v0.4s
157-
; CHECK-NEXT: add v4.4s, v6.4s, v4.4s
158-
; CHECK-NEXT: add v2.4s, v7.4s, v2.4s
159-
; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
160-
; CHECK-NEXT: eor v0.16b, v0.16b, v5.16b
161-
; CHECK-NEXT: eor v2.16b, v2.16b, v7.16b
162-
; CHECK-NEXT: eor v3.16b, v4.16b, v6.16b
163-
; CHECK-NEXT: add v0.4s, v0.4s, v3.4s
164-
; CHECK-NEXT: add v1.4s, v2.4s, v1.4s
147+
; CHECK-NEXT: mov v2.d[1], v16.d[1]
148+
; CHECK-NEXT: mov v3.d[1], v5.d[1]
149+
; CHECK-NEXT: cmlt v7.8h, v0.8h, #0
150+
; CHECK-NEXT: cmlt v1.8h, v4.8h, #0
151+
; CHECK-NEXT: cmlt v6.8h, v2.8h, #0
152+
; CHECK-NEXT: cmlt v5.8h, v3.8h, #0
153+
; CHECK-NEXT: add v0.4s, v7.4s, v0.4s
154+
; CHECK-NEXT: add v4.4s, v1.4s, v4.4s
155+
; CHECK-NEXT: add v2.4s, v6.4s, v2.4s
156+
; CHECK-NEXT: add v3.4s, v5.4s, v3.4s
157+
; CHECK-NEXT: eor v0.16b, v0.16b, v7.16b
158+
; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
159+
; CHECK-NEXT: eor v2.16b, v2.16b, v6.16b
160+
; CHECK-NEXT: eor v3.16b, v3.16b, v5.16b
165161
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
162+
; CHECK-NEXT: add v2.4s, v2.4s, v3.4s
163+
; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
166164
; CHECK-NEXT: addv s0, v0.4s
167165
; CHECK-NEXT: fmov w8, s0
168166
; CHECK-NEXT: lsr w9, w8, #16

‎llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -611,14 +611,14 @@ define void @uzp_v8i16(ptr %a, ptr %b) #1 {
611611
; CHECK-NEXT: ldr q1, [x1]
612612
; CHECK-NEXT: uzp1 v2.8h, v0.8h, v1.8h
613613
; CHECK-NEXT: uzp2 v0.8h, v0.8h, v1.8h
614-
; CHECK-NEXT: add v0.8h, v2.8h, v0.8h
614+
; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
615615
; CHECK-NEXT: str q0, [x0]
616616
; CHECK-NEXT: ret
617617
%tmp1 = load <8 x i16>, ptr %a
618618
%tmp2 = load <8 x i16>, ptr %b
619619
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
620620
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
621-
%tmp5 = add <8 x i16> %tmp3, %tmp4
621+
%tmp5 = xor <8 x i16> %tmp3, %tmp4
622622
store <8 x i16> %tmp5, ptr %a
623623
ret void
624624
}

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