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[RISCV] Combine FP_TO_INT to vfwcvt/fvncvt
Adds new pseudo instructions to make sure that the fcvt instructions have all rounding mode (RM) and unsigned (XU) variants across single-width, widening and narrowing conversions. And likewise, extends the VL patterns to accompany them. We don't add new VL nodes for the widening/narrowing conversions though, instead we just add specific patterns for vfcvts on those wider/narrower types. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D142102
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7 files changed

+409
-805
lines changed

7 files changed

+409
-805
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+122-3
Original file line numberDiff line numberDiff line change
@@ -9580,9 +9580,12 @@ static SDValue performFP_TO_INTCombine(SDNode *N,
95809580
MVT ContainerVT = VT.getSimpleVT();
95819581
SDValue XVal = Src.getOperand(0);
95829582

9583-
// TODO: Support combining with widening and narrowing instructions
9584-
// For now only support conversions of the same bit size
9585-
if (VT.getScalarSizeInBits() != SrcVT.getScalarSizeInBits())
9583+
// For widening and narrowing conversions we just combine it into a
9584+
// VFCVT_..._VL node, as there are no specific VFWCVT/VFNCVT VL nodes. They
9585+
// end up getting lowered to their appropriate pseudo instructions based on
9586+
// their operand types
9587+
if (VT.getScalarSizeInBits() > SrcVT.getScalarSizeInBits() * 2 ||
9588+
VT.getScalarSizeInBits() * 2 < SrcVT.getScalarSizeInBits())
95869589
return SDValue();
95879590

95889591
// Make fixed-length vectors scalable first
@@ -11638,6 +11641,11 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1163811641
return emitQuietFCMP(MI, BB, RISCV::FLE_D, RISCV::FEQ_D, Subtarget);
1163911642
case RISCV::PseudoQuietFLT_D:
1164011643
return emitQuietFCMP(MI, BB, RISCV::FLT_D, RISCV::FEQ_D, Subtarget);
11644+
11645+
// =========================================================================
11646+
// VFCVT
11647+
// =========================================================================
11648+
1164111649
case RISCV::PseudoVFCVT_RM_X_F_V_M1_MASK:
1164211650
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M1_MASK);
1164311651
case RISCV::PseudoVFCVT_RM_X_F_V_M2_MASK:
@@ -11650,6 +11658,7 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1165011658
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_MF2_MASK);
1165111659
case RISCV::PseudoVFCVT_RM_X_F_V_MF4_MASK:
1165211660
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_MF4_MASK);
11661+
1165311662
case RISCV::PseudoVFCVT_RM_XU_F_V_M1_MASK:
1165411663
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_XU_F_V_M1_MASK);
1165511664
case RISCV::PseudoVFCVT_RM_XU_F_V_M2_MASK:
@@ -11662,6 +11671,7 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1166211671
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_XU_F_V_MF2_MASK);
1166311672
case RISCV::PseudoVFCVT_RM_XU_F_V_MF4_MASK:
1166411673
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_XU_F_V_MF4_MASK);
11674+
1166511675
case RISCV::PseudoVFCVT_RM_F_XU_V_M1_MASK:
1166611676
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_XU_V_M1_MASK);
1166711677
case RISCV::PseudoVFCVT_RM_F_XU_V_M2_MASK:
@@ -11674,6 +11684,102 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1167411684
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_XU_V_MF2_MASK);
1167511685
case RISCV::PseudoVFCVT_RM_F_XU_V_MF4_MASK:
1167611686
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_XU_V_MF4_MASK);
11687+
11688+
case RISCV::PseudoVFCVT_RM_F_X_V_M1_MASK:
11689+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_X_V_M1_MASK);
11690+
case RISCV::PseudoVFCVT_RM_F_X_V_M2_MASK:
11691+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_X_V_M2_MASK);
11692+
case RISCV::PseudoVFCVT_RM_F_X_V_M4_MASK:
11693+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_X_V_M4_MASK);
11694+
case RISCV::PseudoVFCVT_RM_F_X_V_M8_MASK:
11695+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_X_V_M8_MASK);
11696+
case RISCV::PseudoVFCVT_RM_F_X_V_MF2_MASK:
11697+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_X_V_MF2_MASK);
11698+
case RISCV::PseudoVFCVT_RM_F_X_V_MF4_MASK:
11699+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_X_V_MF4_MASK);
11700+
11701+
// =========================================================================
11702+
// VFWCVT
11703+
// =========================================================================
11704+
11705+
case RISCV::PseudoVFWCVT_RM_XU_F_V_M1_MASK:
11706+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M1_MASK);
11707+
case RISCV::PseudoVFWCVT_RM_XU_F_V_M2_MASK:
11708+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M2_MASK);
11709+
case RISCV::PseudoVFWCVT_RM_XU_F_V_M4_MASK:
11710+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M4_MASK);
11711+
case RISCV::PseudoVFWCVT_RM_XU_F_V_MF2_MASK:
11712+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_MF2_MASK);
11713+
case RISCV::PseudoVFWCVT_RM_XU_F_V_MF4_MASK:
11714+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_MF4_MASK);
11715+
11716+
case RISCV::PseudoVFWCVT_RM_X_F_V_M1_MASK:
11717+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M1_MASK);
11718+
case RISCV::PseudoVFWCVT_RM_X_F_V_M2_MASK:
11719+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M2_MASK);
11720+
case RISCV::PseudoVFWCVT_RM_X_F_V_M4_MASK:
11721+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M4_MASK);
11722+
case RISCV::PseudoVFWCVT_RM_X_F_V_MF2_MASK:
11723+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_MF2_MASK);
11724+
case RISCV::PseudoVFWCVT_RM_X_F_V_MF4_MASK:
11725+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_MF4_MASK);
11726+
11727+
case RISCV::PseudoVFWCVT_RM_F_XU_V_M1_MASK:
11728+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M1_MASK);
11729+
case RISCV::PseudoVFWCVT_RM_F_XU_V_M2_MASK:
11730+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M2_MASK);
11731+
case RISCV::PseudoVFWCVT_RM_F_XU_V_M4_MASK:
11732+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M4_MASK);
11733+
case RISCV::PseudoVFWCVT_RM_F_XU_V_MF2_MASK:
11734+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF2_MASK);
11735+
case RISCV::PseudoVFWCVT_RM_F_XU_V_MF4_MASK:
11736+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF4_MASK);
11737+
case RISCV::PseudoVFWCVT_RM_F_XU_V_MF8_MASK:
11738+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF8_MASK);
11739+
11740+
case RISCV::PseudoVFWCVT_RM_F_X_V_M1_MASK:
11741+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M1_MASK);
11742+
case RISCV::PseudoVFWCVT_RM_F_X_V_M2_MASK:
11743+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M2_MASK);
11744+
case RISCV::PseudoVFWCVT_RM_F_X_V_M4_MASK:
11745+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M4_MASK);
11746+
case RISCV::PseudoVFWCVT_RM_F_X_V_MF2_MASK:
11747+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF2_MASK);
11748+
case RISCV::PseudoVFWCVT_RM_F_X_V_MF4_MASK:
11749+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF4_MASK);
11750+
case RISCV::PseudoVFWCVT_RM_F_X_V_MF8_MASK:
11751+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF8_MASK);
11752+
11753+
// =========================================================================
11754+
// VFNCVT
11755+
// =========================================================================
11756+
11757+
case RISCV::PseudoVFNCVT_RM_XU_F_W_M1_MASK:
11758+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M1_MASK);
11759+
case RISCV::PseudoVFNCVT_RM_XU_F_W_M2_MASK:
11760+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M2_MASK);
11761+
case RISCV::PseudoVFNCVT_RM_XU_F_W_M4_MASK:
11762+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M4_MASK);
11763+
case RISCV::PseudoVFNCVT_RM_XU_F_W_MF2_MASK:
11764+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_MF2_MASK);
11765+
case RISCV::PseudoVFNCVT_RM_XU_F_W_MF4_MASK:
11766+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_MF4_MASK);
11767+
case RISCV::PseudoVFNCVT_RM_XU_F_W_MF8_MASK:
11768+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_MF8_MASK);
11769+
11770+
case RISCV::PseudoVFNCVT_RM_X_F_W_M1_MASK:
11771+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M1_MASK);
11772+
case RISCV::PseudoVFNCVT_RM_X_F_W_M2_MASK:
11773+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M2_MASK);
11774+
case RISCV::PseudoVFNCVT_RM_X_F_W_M4_MASK:
11775+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M4_MASK);
11776+
case RISCV::PseudoVFNCVT_RM_X_F_W_MF2_MASK:
11777+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_MF2_MASK);
11778+
case RISCV::PseudoVFNCVT_RM_X_F_W_MF4_MASK:
11779+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_MF4_MASK);
11780+
case RISCV::PseudoVFNCVT_RM_X_F_W_MF8_MASK:
11781+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_MF8_MASK);
11782+
1167711783
case RISCV::PseudoVFNCVT_RM_F_XU_W_M1_MASK:
1167811784
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_M1_MASK);
1167911785
case RISCV::PseudoVFNCVT_RM_F_XU_W_M2_MASK:
@@ -11684,6 +11790,18 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1168411790
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_MF2_MASK);
1168511791
case RISCV::PseudoVFNCVT_RM_F_XU_W_MF4_MASK:
1168611792
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_MF4_MASK);
11793+
11794+
case RISCV::PseudoVFNCVT_RM_F_X_W_M1_MASK:
11795+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_M1_MASK);
11796+
case RISCV::PseudoVFNCVT_RM_F_X_W_M2_MASK:
11797+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_M2_MASK);
11798+
case RISCV::PseudoVFNCVT_RM_F_X_W_M4_MASK:
11799+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_M4_MASK);
11800+
case RISCV::PseudoVFNCVT_RM_F_X_W_MF2_MASK:
11801+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_MF2_MASK);
11802+
case RISCV::PseudoVFNCVT_RM_F_X_W_MF4_MASK:
11803+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_MF4_MASK);
11804+
1168711805
case RISCV::PseudoVFROUND_NOEXCEPT_V_M1_MASK:
1168811806
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M1_MASK,
1168911807
RISCV::PseudoVFCVT_F_X_V_M1_MASK);
@@ -13283,6 +13401,7 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
1328313401
NODE_NAME_CASE(SINT_TO_FP_VL)
1328413402
NODE_NAME_CASE(UINT_TO_FP_VL)
1328513403
NODE_NAME_CASE(VFCVT_RM_F_XU_VL)
13404+
NODE_NAME_CASE(VFCVT_RM_F_X_VL)
1328613405
NODE_NAME_CASE(FP_EXTEND_VL)
1328713406
NODE_NAME_CASE(FP_ROUND_VL)
1328813407
NODE_NAME_CASE(VWMUL_VL)

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

+1
Original file line numberDiff line numberDiff line change
@@ -245,6 +245,7 @@ enum NodeType : unsigned {
245245
VFCVT_RM_XU_F_VL, // Has a rounding mode operand.
246246
SINT_TO_FP_VL,
247247
UINT_TO_FP_VL,
248+
VFCVT_RM_F_X_VL, // Has a rounding mode operand.
248249
VFCVT_RM_F_XU_VL, // Has a rounding mode operand.
249250
FP_ROUND_VL,
250251
FP_EXTEND_VL,

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

+61-4
Original file line numberDiff line numberDiff line change
@@ -3435,6 +3435,18 @@ multiclass VPseudoVWCVTI_V {
34353435
}
34363436
}
34373437

3438+
multiclass VPseudoVWCVTI_RM_V {
3439+
defvar constraint = "@earlyclobber $rd";
3440+
foreach m = MxListFW in {
3441+
defvar mx = m.MX;
3442+
defvar WriteVFWCvtFToIV_MX = !cast<SchedWrite>("WriteVFWCvtFToIV_" # mx);
3443+
defvar ReadVFWCvtFToIV_MX = !cast<SchedRead>("ReadVFWCvtFToIV_" # mx);
3444+
3445+
defm _V : VPseudoConversionRM<m.wvrclass, m.vrclass, m, constraint>,
3446+
Sched<[WriteVFWCvtFToIV_MX, ReadVFWCvtFToIV_MX, ReadVMask]>;
3447+
}
3448+
}
3449+
34383450
multiclass VPseudoVWCVTF_V {
34393451
defvar constraint = "@earlyclobber $rd";
34403452
foreach m = MxListW in {
@@ -3447,6 +3459,18 @@ multiclass VPseudoVWCVTF_V {
34473459
}
34483460
}
34493461

3462+
multiclass VPseudoVWCVTF_RM_V {
3463+
defvar constraint = "@earlyclobber $rd";
3464+
foreach m = MxListW in {
3465+
defvar mx = m.MX;
3466+
defvar WriteVFWCvtIToFV_MX = !cast<SchedWrite>("WriteVFWCvtIToFV_" # mx);
3467+
defvar ReadVFWCvtIToFV_MX = !cast<SchedRead>("ReadVFWCvtIToFV_" # mx);
3468+
3469+
defm _V : VPseudoConversionRM<m.wvrclass, m.vrclass, m, constraint>,
3470+
Sched<[WriteVFWCvtIToFV_MX, ReadVFWCvtIToFV_MX, ReadVMask]>;
3471+
}
3472+
}
3473+
34503474
multiclass VPseudoVWCVTD_V {
34513475
defvar constraint = "@earlyclobber $rd";
34523476
foreach m = MxListFW in {
@@ -3471,6 +3495,18 @@ multiclass VPseudoVNCVTI_W {
34713495
}
34723496
}
34733497

3498+
multiclass VPseudoVNCVTI_RM_W {
3499+
defvar constraint = "@earlyclobber $rd";
3500+
foreach m = MxListW in {
3501+
defvar mx = m.MX;
3502+
defvar WriteVFNCvtFToIV_MX = !cast<SchedWrite>("WriteVFNCvtFToIV_" # mx);
3503+
defvar ReadVFNCvtFToIV_MX = !cast<SchedRead>("ReadVFNCvtFToIV_" # mx);
3504+
3505+
defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint>,
3506+
Sched<[WriteVFNCvtFToIV_MX, ReadVFNCvtFToIV_MX, ReadVMask]>;
3507+
}
3508+
}
3509+
34743510
multiclass VPseudoVNCVTF_W {
34753511
defvar constraint = "@earlyclobber $rd";
34763512
foreach m = MxListFW in {
@@ -5510,16 +5546,20 @@ let Uses = [FRM] in {
55105546
defm PseudoVFCVT_XU_F : VPseudoVCVTI_V;
55115547
defm PseudoVFCVT_X_F : VPseudoVCVTI_V;
55125548
}
5513-
defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V;
5514-
defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V;
5549+
55155550
defm PseudoVFCVT_RM_XU_F : VPseudoVCVTI_RM_V;
55165551
defm PseudoVFCVT_RM_X_F : VPseudoVCVTI_RM_V;
5552+
5553+
defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V;
5554+
defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V;
5555+
55175556
defm PseudoVFROUND_NOEXCEPT : VPseudoVFROUND_NOEXCEPT_V;
55185557
let Uses = [FRM] in {
55195558
defm PseudoVFCVT_F_XU : VPseudoVCVTF_V;
55205559
defm PseudoVFCVT_F_X : VPseudoVCVTF_V;
55215560
}
55225561
defm PseudoVFCVT_RM_F_XU : VPseudoVCVTF_RM_V;
5562+
defm PseudoVFCVT_RM_F_X : VPseudoVCVTF_RM_V;
55235563
} // mayRaiseFPException = true
55245564

55255565
//===----------------------------------------------------------------------===//
@@ -5530,10 +5570,19 @@ let Uses = [FRM] in {
55305570
defm PseudoVFWCVT_XU_F : VPseudoVWCVTI_V;
55315571
defm PseudoVFWCVT_X_F : VPseudoVWCVTI_V;
55325572
}
5573+
defm PseudoVFWCVT_RM_XU_F : VPseudoVWCVTI_RM_V;
5574+
defm PseudoVFWCVT_RM_X_F : VPseudoVWCVTI_RM_V;
5575+
55335576
defm PseudoVFWCVT_RTZ_XU_F : VPseudoVWCVTI_V;
55345577
defm PseudoVFWCVT_RTZ_X_F : VPseudoVWCVTI_V;
5578+
5579+
let Uses = [FRM] in {
55355580
defm PseudoVFWCVT_F_XU : VPseudoVWCVTF_V;
55365581
defm PseudoVFWCVT_F_X : VPseudoVWCVTF_V;
5582+
}
5583+
defm PseudoVFWCVT_RM_F_XU : VPseudoVWCVTF_RM_V;
5584+
defm PseudoVFWCVT_RM_F_X : VPseudoVWCVTF_RM_V;
5585+
55375586
defm PseudoVFWCVT_F_F : VPseudoVWCVTD_V;
55385587
} // mayRaiseFPException = true
55395588

@@ -5545,15 +5594,23 @@ let Uses = [FRM] in {
55455594
defm PseudoVFNCVT_XU_F : VPseudoVNCVTI_W;
55465595
defm PseudoVFNCVT_X_F : VPseudoVNCVTI_W;
55475596
}
5597+
defm PseudoVFNCVT_RM_XU_F : VPseudoVNCVTI_RM_W;
5598+
defm PseudoVFNCVT_RM_X_F : VPseudoVNCVTI_RM_W;
5599+
55485600
defm PseudoVFNCVT_RTZ_XU_F : VPseudoVNCVTI_W;
55495601
defm PseudoVFNCVT_RTZ_X_F : VPseudoVNCVTI_W;
5602+
55505603
let Uses = [FRM] in {
55515604
defm PseudoVFNCVT_F_XU : VPseudoVNCVTF_W;
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defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W;
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defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W;
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}
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defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W;
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defm PseudoVFNCVT_RM_F_XU : VPseudoVNCVTF_RM_W;
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defm PseudoVFNCVT_RM_F_X : VPseudoVNCVTF_RM_W;
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let Uses = [FRM] in
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defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W;
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defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W;
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} // mayRaiseFPException = true
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} // Predicates = [HasVInstructionsAnyF]
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