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[llvm] Construct SmallVector<SDValue> with ArrayRef (NFC) (#102578)
1 parent 8f21ff9 commit f4fb735

15 files changed

+32
-34
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -15720,7 +15720,7 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
1572015720

1572115721
// Finally, recreate the node, it's operands were updated to use
1572215722
// frozen operands, so we just need to use it's "original" operands.
15723-
SmallVector<SDValue> Ops(N0->op_begin(), N0->op_end());
15723+
SmallVector<SDValue> Ops(N0->ops());
1572415724
// Special-handle ISD::UNDEF, each single one of them can be it's own thing.
1572515725
for (SDValue &Op : Ops) {
1572615726
if (Op.getOpcode() == ISD::UNDEF)
@@ -24160,7 +24160,7 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
2416024160
if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse() &&
2416124161
!(LegalDAG && In.getValueType().isScalableVector())) {
2416224162
unsigned NumOps = N->getNumOperands() * In.getNumOperands();
24163-
SmallVector<SDValue, 4> Ops(In->op_begin(), In->op_end());
24163+
SmallVector<SDValue, 4> Ops(In->ops());
2416424164
Ops.resize(NumOps, DAG.getUNDEF(Ops[0].getValueType()));
2416524165
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
2416624166
}
@@ -26612,7 +26612,7 @@ SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
2661226612
N0.getOperand(0).getValueType().isScalableVector() ==
2661326613
N1.getValueType().isScalableVector()) {
2661426614
unsigned Factor = N1.getValueType().getVectorMinNumElements();
26615-
SmallVector<SDValue, 8> Ops(N0->op_begin(), N0->op_end());
26615+
SmallVector<SDValue, 8> Ops(N0->ops());
2661626616
Ops[InsIdx / Factor] = N1;
2661726617
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
2661826618
}

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1449,8 +1449,7 @@ SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
14491449

14501450
// We introduced a cycle though, so update the loads operands, making sure
14511451
// to use the original store's chain as an incoming chain.
1452-
SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1453-
NewLoad->op_end());
1452+
SmallVector<SDValue, 6> NewLoadOperands(NewLoad->ops());
14541453
NewLoadOperands[0] = Ch;
14551454
NewLoad =
14561455
SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2375,7 +2375,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
23752375
// The Mask. Update in place.
23762376
EVT DataVT = DataOp.getValueType();
23772377
Mask = PromoteTargetBoolean(Mask, DataVT);
2378-
SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
2378+
SmallVector<SDValue, 4> NewOps(N->ops());
23792379
NewOps[4] = Mask;
23802380
return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
23812381
}
@@ -2394,7 +2394,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
23942394
assert(OpNo == 3 && "Only know how to promote the mask!");
23952395
EVT DataVT = N->getValueType(0);
23962396
SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
2397-
SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
2397+
SmallVector<SDValue, 4> NewOps(N->ops());
23982398
NewOps[OpNo] = Mask;
23992399
SDNode *Res = DAG.UpdateNodeOperands(N, NewOps);
24002400
if (Res == N)
@@ -2408,7 +2408,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
24082408

24092409
SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
24102410
unsigned OpNo) {
2411-
SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
2411+
SmallVector<SDValue, 5> NewOps(N->ops());
24122412

24132413
if (OpNo == 2) {
24142414
// The Mask
@@ -2437,7 +2437,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
24372437
SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
24382438
unsigned OpNo) {
24392439
bool TruncateStore = N->isTruncatingStore();
2440-
SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
2440+
SmallVector<SDValue, 5> NewOps(N->ops());
24412441

24422442
if (OpNo == 2) {
24432443
// The Mask
@@ -2670,7 +2670,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
26702670
SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
26712671
SDLoc DL(N);
26722672
SDValue Op = N->getOperand(OpNo);
2673-
SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
2673+
SmallVector<SDValue, 4> NewOps(N->ops());
26742674

26752675
if (OpNo == 2) { // Mask
26762676
// Update in place.
@@ -2726,14 +2726,14 @@ SDValue DAGTypeLegalizer::PromoteIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
27262726
assert((N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD && OpNo == 3) ||
27272727
(N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
27282728

2729-
SmallVector<SDValue, 8> NewOps(N->op_begin(), N->op_end());
2729+
SmallVector<SDValue, 8> NewOps(N->ops());
27302730
NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
27312731

27322732
return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
27332733
}
27342734

27352735
SDValue DAGTypeLegalizer::PromoteIntOp_VP_SPLICE(SDNode *N, unsigned OpNo) {
2736-
SmallVector<SDValue, 6> NewOps(N->op_begin(), N->op_end());
2736+
SmallVector<SDValue, 6> NewOps(N->ops());
27372737

27382738
if (OpNo == 2) { // Offset operand
27392739
NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
@@ -5702,7 +5702,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_VP_STRIDED(SDNode *N, unsigned OpNo) {
57025702
(N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE && OpNo == 4));
57035703

57045704
SDValue Hi; // The upper half is dropped out.
5705-
SmallVector<SDValue, 8> NewOps(N->op_begin(), N->op_end());
5705+
SmallVector<SDValue, 8> NewOps(N->ops());
57065706
GetExpandedInteger(NewOps[OpNo], NewOps[OpNo], Hi);
57075707

57085708
return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5174,7 +5174,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_XRINT(SDNode *N) {
51745174
SDValue DAGTypeLegalizer::WidenVecRes_Convert_StrictFP(SDNode *N) {
51755175
SDValue InOp = N->getOperand(1);
51765176
SDLoc DL(N);
5177-
SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
5177+
SmallVector<SDValue, 4> NewOps(N->ops());
51785178

51795179
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
51805180
unsigned WidenNumElts = WidenVT.getVectorNumElements();
@@ -5469,7 +5469,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
54695469
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
54705470
unsigned WidenNumElts = WidenVT.getVectorNumElements();
54715471

5472-
SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
5472+
SmallVector<SDValue, 16> NewOps(N->ops());
54735473
assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
54745474
NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
54755475

@@ -6664,7 +6664,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
66646664
unsigned NumElts = VT.getVectorNumElements();
66656665
SmallVector<SDValue, 16> Ops(NumElts);
66666666
if (N->isStrictFPOpcode()) {
6667-
SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
6667+
SmallVector<SDValue, 4> NewOps(N->ops());
66686668
SmallVector<SDValue, 32> OpChains;
66696669
for (unsigned i=0; i < NumElts; ++i) {
66706670
NewOps[1] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,

‎llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,7 @@ static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
143143
// Helper for AddGlue to clone node operands.
144144
static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs,
145145
SDValue ExtraOper = SDValue()) {
146-
SmallVector<SDValue, 8> Ops(N->op_begin(), N->op_end());
146+
SmallVector<SDValue, 8> Ops(N->ops());
147147
if (ExtraOper.getNode())
148148
Ops.push_back(ExtraOper);
149149

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3245,7 +3245,7 @@ bool TargetLowering::SimplifyDemandedVectorElts(
32453245
// Don't simplify BROADCASTS.
32463246
if (llvm::any_of(Op->op_values(),
32473247
[&](SDValue Elt) { return Op.getOperand(0) != Elt; })) {
3248-
SmallVector<SDValue, 32> Ops(Op->op_begin(), Op->op_end());
3248+
SmallVector<SDValue, 32> Ops(Op->ops());
32493249
bool Updated = false;
32503250
for (unsigned i = 0; i != NumElts; ++i) {
32513251
if (!DemandedElts[i] && !Ops[i].isUndef()) {

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14546,7 +14546,7 @@ SDValue AArch64TargetLowering::LowerCONCAT_VECTORS(SDValue Op,
1454614546
return Op;
1454714547

1454814548
// Concat each pair of subvectors and pack into the lower half of the array.
14549-
SmallVector<SDValue> ConcatOps(Op->op_begin(), Op->op_end());
14549+
SmallVector<SDValue> ConcatOps(Op->ops());
1455014550
while (ConcatOps.size() > 1) {
1455114551
for (unsigned I = 0, E = ConcatOps.size(); I != E; I += 2) {
1455214552
SDValue V1 = ConcatOps[I];
@@ -25041,7 +25041,7 @@ static SDValue legalizeSVEGatherPrefetchOffsVec(SDNode *N, SelectionDAG &DAG) {
2504125041
// Extend the unpacked offset vector to 64-bit lanes.
2504225042
SDLoc DL(N);
2504325043
Offset = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::nxv2i64, Offset);
25044-
SmallVector<SDValue, 5> Ops(N->op_begin(), N->op_end());
25044+
SmallVector<SDValue, 5> Ops(N->ops());
2504525045
// Replace the offset operand with the 64-bit one.
2504625046
Ops[OffsetPos] = Offset;
2504725047

@@ -25061,7 +25061,7 @@ static SDValue combineSVEPrefetchVecBaseImmOff(SDNode *N, SelectionDAG &DAG,
2506125061
return SDValue();
2506225062

2506325063
// ...otherwise swap the offset base with the offset...
25064-
SmallVector<SDValue, 5> Ops(N->op_begin(), N->op_end());
25064+
SmallVector<SDValue, 5> Ops(N->ops());
2506525065
std::swap(Ops[ImmPos], Ops[OffsetPos]);
2506625066
// ...and remap the intrinsic `aarch64_sve_prf<T>_gather_scalar_offset` to
2506725067
// `aarch64_sve_prfb_gather_uxtw_index`.

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2788,7 +2788,7 @@ void AMDGPUDAGToDAGISel::SelectINTRINSIC_WO_CHAIN(SDNode *N) {
27882788
}
27892789

27902790
if (ConvGlueNode) {
2791-
SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
2791+
SmallVector<SDValue, 4> NewOps(N->ops());
27922792
NewOps.push_back(SDValue(ConvGlueNode, 0));
27932793
CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), NewOps);
27942794
}

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4957,7 +4957,7 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
49574957
SDValue CastBack =
49584958
DAG.getNode(ISD::BITCAST, SL, HighBits.getValueType(), NegHi);
49594959

4960-
SmallVector<SDValue, 8> Ops(BCSrc->op_begin(), BCSrc->op_end());
4960+
SmallVector<SDValue, 8> Ops(BCSrc->ops());
49614961
Ops.back() = CastBack;
49624962
DCI.AddToWorklist(NegHi.getNode());
49634963
SDValue Build =

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11383,7 +11383,7 @@ SDValue SITargetLowering::performMemSDNodeCombine(MemSDNode *N,
1138311383
SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), N->getAddressSpace(),
1138411384
N->getMemoryVT(), DCI);
1138511385
if (NewPtr) {
11386-
SmallVector<SDValue, 8> NewOps(N->op_begin(), N->op_end());
11386+
SmallVector<SDValue, 8> NewOps(N->ops());
1138711387

1138811388
NewOps[PtrIdx] = NewPtr;
1138911389
return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
@@ -15103,7 +15103,7 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1510315103
} else
1510415104
break;
1510515105

15106-
SmallVector<SDValue, 9> Ops(Node->op_begin(), Node->op_end());
15106+
SmallVector<SDValue, 9> Ops(Node->ops());
1510715107
Ops[1] = Src0;
1510815108
Ops[3] = Src1;
1510915109
Ops[5] = Src2;

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9219,7 +9219,7 @@ static SDValue LowerCONCAT_VECTORS_i1(SDValue Op, SelectionDAG &DAG,
92199219
};
92209220

92219221
// Concat each pair of subvectors and pack into the lower half of the array.
9222-
SmallVector<SDValue> ConcatOps(Op->op_begin(), Op->op_end());
9222+
SmallVector<SDValue> ConcatOps(Op->ops());
92239223
while (ConcatOps.size() > 1) {
92249224
for (unsigned I = 0, E = ConcatOps.size(); I != E; I += 2) {
92259225
SDValue V1 = ConcatOps[I];

‎llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6143,7 +6143,7 @@ static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
61436143
}
61446144

61456145
// Copy regular operands
6146-
SmallVector<SDValue, 8> OtherOps(N->op_begin(), N->op_end());
6146+
SmallVector<SDValue, 8> OtherOps(N->ops());
61476147

61486148
// The select routine does not have access to the LoadSDNode instance, so
61496149
// pass along the extension information
@@ -6300,7 +6300,7 @@ static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
63006300
"Custom handling of non-i8 ldu/ldg?");
63016301

63026302
// Just copy all operands as-is
6303-
SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
6303+
SmallVector<SDValue, 4> Ops(N->ops());
63046304

63056305
// Force output to i16
63066306
SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14344,8 +14344,7 @@ SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
1434414344
continue;
1434514345
}
1434614346

14347-
SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
14348-
PromOp.getNode()->op_end());
14347+
SmallVector<SDValue, 3> Ops(PromOp.getNode()->ops());
1434914348

1435014349
// If there are any constant inputs, make sure they're replaced now.
1435114350
for (unsigned i = 0; i < 2; ++i)

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4080,7 +4080,7 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
40804080
// of the component build_vectors. We eagerly lower to scalable and
40814081
// insert_subvector here to avoid DAG combining it back to a large
40824082
// build_vector.
4083-
SmallVector<SDValue> BuildVectorOps(Op->op_begin(), Op->op_end());
4083+
SmallVector<SDValue> BuildVectorOps(Op->ops());
40844084
unsigned NumOpElts = M1VT.getVectorMinNumElements();
40854085
SDValue Vec = DAG.getUNDEF(ContainerVT);
40864086
for (unsigned i = 0; i < VT.getVectorNumElements(); i += ElemsPerVReg) {
@@ -8782,7 +8782,7 @@ static SDValue lowerVectorIntrinsicScalars(SDValue Op, SelectionDAG &DAG,
87828782
unsigned SplatOp = II->ScalarOperand + 1 + HasChain;
87838783
assert(SplatOp < Op.getNumOperands());
87848784

8785-
SmallVector<SDValue, 8> Operands(Op->op_begin(), Op->op_end());
8785+
SmallVector<SDValue, 8> Operands(Op->ops());
87868786
SDValue &ScalarOp = Operands[SplatOp];
87878787
MVT OpVT = ScalarOp.getSimpleValueType();
87888788
MVT XLenVT = Subtarget.getXLenVT();

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -43944,7 +43944,7 @@ static SDValue combineBitcast(SDNode *N, SelectionDAG &DAG,
4394443944
if (ISD::isBuildVectorAllZeros(LastOp.getNode())) {
4394543945
SrcVT = LastOp.getValueType();
4394643946
unsigned NumConcats = 8 / SrcVT.getVectorNumElements();
43947-
SmallVector<SDValue, 4> Ops(N0->op_begin(), N0->op_end());
43947+
SmallVector<SDValue, 4> Ops(N0->ops());
4394843948
Ops.resize(NumConcats, DAG.getConstant(0, dl, SrcVT));
4394943949
N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
4395043950
N0 = DAG.getBitcast(MVT::i8, N0);
@@ -56785,7 +56785,7 @@ static SDValue combineCONCAT_VECTORS(SDNode *N, SelectionDAG &DAG,
5678556785
EVT VT = N->getValueType(0);
5678656786
EVT SrcVT = N->getOperand(0).getValueType();
5678756787
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
56788-
SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
56788+
SmallVector<SDValue, 4> Ops(N->ops());
5678956789

5679056790
if (VT.getVectorElementType() == MVT::i1) {
5679156791
// Attempt to constant fold.

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