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[RISCV] Consolidate some DecoderNamespaces for standard extensions. (#128954)
First thing to know is that the subtarget feature checks used to block accessing a decoder table are only a performance optimization and not required for functionality. The tables have their own predicate checks. I've removed them from all the standard extension tables. -RV32 Zacas decoder namespace has been renamed to RV32GPRPair, I think Zilsd(rv32 load/store pair) can go in here too. -The RV32 Zdinx table has been renamed to also use RV32GPRPair. -The Zfinx table has been renamed to remove superflous "RV" prefix. -Zcmp and Zcmt tables have been combined into a ZcOverlap table. I think Zclsd(rv32 compressed load/store pair) can go in here too. -All the extra standard extension tables are checked after the main standard extension table. This makes the common case of the main table matching occur earlier. -Zicfiss is the exception to this as it needs to be checked before the main table since it overrides some encodings from Zcmop. This can't be handled by a predicate based priority as Zicfiss only overrides a subset of Zcmop encodings.
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‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 13 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -657,16 +657,6 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
657657

658658
uint32_t Insn = support::endian::read32le(Bytes.data());
659659

660-
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
661-
!STI.hasFeature(RISCV::Feature64Bit),
662-
DecoderTableRV32Zdinx32,
663-
"RV32Zdinx (Double in Integer and rv32)");
664-
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZacas) &&
665-
!STI.hasFeature(RISCV::Feature64Bit),
666-
DecoderTableRV32Zacas32,
667-
"RV32Zacas (Compare-And-Swap and rv32)");
668-
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
669-
"RVZfinx (Float in Integer)");
670660
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
671661
DecoderTableXVentana32, "XVentanaCondOps");
672662
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
@@ -721,6 +711,11 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
721711
TRY_TO_DECODE_FEATURE_ANY(XRivosFeatureGroup, DecoderTableXRivos32, "Rivos");
722712

723713
TRY_TO_DECODE(true, DecoderTable32, "RISCV32");
714+
TRY_TO_DECODE(true, DecoderTableRV32GPRPair32,
715+
"RV32GPRPair (rv32 and GPR pairs)");
716+
TRY_TO_DECODE(true, DecoderTableZfinx32, "Zfinx (Float in Integer)");
717+
TRY_TO_DECODE(true, DecoderTableZdinxRV32GPRPair32,
718+
"ZdinxRV32GPRPair (rv32 and Double in Integer)");
724719

725720
return MCDisassembler::Fail;
726721
}
@@ -736,15 +731,6 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
736731
Size = 2;
737732

738733
uint32_t Insn = support::endian::read16le(Bytes.data());
739-
TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit),
740-
DecoderTableRISCV32Only_16,
741-
"RISCV32Only_16 (16-bit Instruction)");
742-
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZicfiss, DecoderTableZicfiss16,
743-
"RVZicfiss (Shadow Stack)");
744-
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZcmt, DecoderTableRVZcmt16,
745-
"Zcmt (16-bit Table Jump Instructions)");
746-
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
747-
"Zcmp (16-bit Push/Pop & Double Move Instructions)");
748734

749735
TRY_TO_DECODE_FEATURE_ANY(XqciFeatureGroup, DecoderTableXqci16,
750736
"Qualcomm uC 16bit");
@@ -753,8 +739,16 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
753739
"Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)");
754740
TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureVendorXwchc),
755741
DecoderTableXwchc16, "WCH QingKe XW");
742+
743+
// DecoderTableZicfiss16 must be checked before DecoderTable16.
744+
TRY_TO_DECODE(true, DecoderTableZicfiss16, "RVZicfiss (Shadow Stack)");
756745
TRY_TO_DECODE_AND_ADD_SP(true, DecoderTable16,
757746
"RISCV_C (16-bit Instruction)");
747+
TRY_TO_DECODE_AND_ADD_SP(true, DecoderTableRISCV32Only_16,
748+
"RISCV32Only_16 (16-bit Instruction)");
749+
// Zc* instructions incompatible with Zcf or Zcd.
750+
TRY_TO_DECODE(true, DecoderTableZcOverlap16,
751+
"ZcOverlap (16-bit Instructions overlapping with Zcf/Zcd)");
758752

759753
return MCDisassembler::Fail;
760754
}

‎llvm/lib/Target/RISCV/RISCVInstrInfoD.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -60,9 +60,9 @@ def FPR64IN32X : RegisterOperand<GPRPair> {
6060

6161
def DExt : ExtInfo<"", "", [HasStdExtD], f64, FPR64, FPR32, FPR64, ?>;
6262

63-
def ZdinxExt : ExtInfo<"_INX", "RVZfinx", [HasStdExtZdinx, IsRV64],
63+
def ZdinxExt : ExtInfo<"_INX", "Zfinx", [HasStdExtZdinx, IsRV64],
6464
f64, FPR64INX, FPR32INX, FPR64INX, ?>;
65-
def Zdinx32Ext : ExtInfo<"_IN32X", "RV32Zdinx", [HasStdExtZdinx, IsRV32],
65+
def Zdinx32Ext : ExtInfo<"_IN32X", "ZdinxRV32GPRPair", [HasStdExtZdinx, IsRV32],
6666
f64, FPR64IN32X, FPR32INX, FPR64IN32X, ?>;
6767

6868
defvar DExts = [DExt, ZdinxExt, Zdinx32Ext];

‎llvm/lib/Target/RISCV/RISCVInstrInfoF.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,7 @@ class ExtInfo<string suffix, string space, list<Predicate> predicates,
116116

117117
def FExt : ExtInfo<"", "", [HasStdExtF], f32, FPR32, FPR32, ?, ?>;
118118

119-
def ZfinxExt : ExtInfo<"_INX", "RVZfinx", [HasStdExtZfinx], f32, FPR32INX, FPR32INX, ?, ?>;
119+
def ZfinxExt : ExtInfo<"_INX", "Zfinx", [HasStdExtZfinx], f32, FPR32INX, FPR32INX, ?, ?>;
120120

121121
defvar FExts = [FExt, ZfinxExt];
122122

‎llvm/lib/Target/RISCV/RISCVInstrInfoZa.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ let Predicates = [HasStdExtZacas], IsSignExtendingOpW = 1 in {
5959
defm AMOCAS_W : AMO_cas_aq_rl<0b00101, 0b010, "amocas.w", GPR>;
6060
} // Predicates = [HasStdExtZacas]
6161

62-
let Predicates = [HasStdExtZacas, IsRV32], DecoderNamespace = "RV32Zacas" in {
62+
let Predicates = [HasStdExtZacas, IsRV32], DecoderNamespace = "RV32GPRPair" in {
6363
defm AMOCAS_D_RV32 : AMO_cas_aq_rl<0b00101, 0b011, "amocas.d", GPRPairRV32>;
6464
} // Predicates = [HasStdExtZacas, IsRV32]
6565

‎llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -216,7 +216,7 @@ def C_SH_INX : CStoreH_rri<0b100011, 0b0, "c.sh", GPRF16C>,
216216
} // Predicates = [HasStdExtZcb]
217217

218218
// Zcmp
219-
let DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp],
219+
let DecoderNamespace = "ZcOverlap", Predicates = [HasStdExtZcmp],
220220
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
221221
let Defs = [X10, X11] in
222222
def CM_MVA01S : RVInst16CA<0b101011, 0b11, 0b10, (outs),
@@ -227,9 +227,9 @@ let Uses = [X10, X11] in
227227
def CM_MVSA01 : RVInst16CA<0b101011, 0b01, 0b10, (outs SR07:$rs1, SR07:$rs2),
228228
(ins), "cm.mvsa01", "$rs1, $rs2">,
229229
Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>;
230-
} // DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp]...
230+
} // DecoderNamespace = "ZcOverlap", Predicates = [HasStdExtZcmp]...
231231

232-
let DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp] in {
232+
let DecoderNamespace = "ZcOverlap", Predicates = [HasStdExtZcmp] in {
233233
let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Uses = [X2], Defs = [X2] in
234234
def CM_PUSH : RVInstZcCPPP<0b11000, "cm.push", negstackadj>,
235235
Sched<[WriteIALU, ReadIALU, ReadStoreData, ReadStoreData,
@@ -258,9 +258,9 @@ def CM_POP : RVInstZcCPPP<0b11010, "cm.pop">,
258258
Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
259259
WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
260260
WriteLDW, WriteLDW, WriteLDW, ReadIALU]>;
261-
} // DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp]...
261+
} // DecoderNamespace = "ZcOverlap", Predicates = [HasStdExtZcmp]...
262262

263-
let DecoderNamespace = "RVZcmt", Predicates = [HasStdExtZcmt],
263+
let DecoderNamespace = "ZcOverlap", Predicates = [HasStdExtZcmt],
264264
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
265265
def CM_JT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm5:$index),
266266
"cm.jt", "$index">{
@@ -278,7 +278,7 @@ def CM_JALT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm8ge32:$index),
278278
let Inst{12-10} = 0b000;
279279
let Inst{9-2} = index;
280280
}
281-
} // DecoderNamespace = "RVZcmt", Predicates = [HasStdExtZcmt]...
281+
} // DecoderNamespace = "ZcOverlap", Predicates = [HasStdExtZcmt]...
282282

283283

284284
let Predicates = [HasStdExtZcb, HasStdExtZmmul] in{

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -52,22 +52,22 @@ def ZfhDExt : ExtInfo<"", "", [HasStdExtZfh, HasStdExtD],
5252
def ZfhminDExt : ExtInfo<"", "", [HasStdExtZfhmin, HasStdExtD],
5353
?, ?, FPR32, FPR64, FPR16>;
5454

55-
def ZhinxExt : ExtInfo<"_INX", "RVZfinx",
55+
def ZhinxExt : ExtInfo<"_INX", "Zfinx",
5656
[HasStdExtZhinx],
5757
f16, FPR16INX, FPR32INX, ?, FPR16INX>;
58-
def ZhinxminExt : ExtInfo<"_INX", "RVZfinx",
58+
def ZhinxminExt : ExtInfo<"_INX", "Zfinx",
5959
[HasStdExtZhinxmin],
6060
f16, FPR16INX, FPR32INX, ?, FPR16INX>;
61-
def ZhinxZdinxExt : ExtInfo<"_INX", "RVZfinx",
61+
def ZhinxZdinxExt : ExtInfo<"_INX", "Zfinx",
6262
[HasStdExtZhinx, HasStdExtZdinx, IsRV64],
6363
?, ?, FPR32INX, FPR64INX, FPR16INX>;
64-
def ZhinxminZdinxExt : ExtInfo<"_INX", "RVZfinx",
64+
def ZhinxminZdinxExt : ExtInfo<"_INX", "Zfinx",
6565
[HasStdExtZhinxmin, HasStdExtZdinx, IsRV64],
6666
?, ?, FPR32INX, FPR64INX, FPR16INX>;
67-
def ZhinxZdinx32Ext : ExtInfo<"_IN32X", "RV32Zdinx",
67+
def ZhinxZdinx32Ext : ExtInfo<"_IN32X", "ZdinxGPRPairRV32",
6868
[HasStdExtZhinx, HasStdExtZdinx, IsRV32],
6969
?, ?, FPR32INX, FPR64IN32X, FPR16INX >;
70-
def ZhinxminZdinx32Ext : ExtInfo<"_IN32X", "RV32Zdinx",
70+
def ZhinxminZdinx32Ext : ExtInfo<"_IN32X", "ZdinxGPRPairRV32",
7171
[HasStdExtZhinxmin, HasStdExtZdinx, IsRV32],
7272
?, ?, FPR32INX, FPR64IN32X, FPR16INX>;
7373

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