[SLP]Fix PR91309: Do not consider SExt as always producing signed result.

Still need to do the full analysis of the signedness of the values
rather than rely on Instruction opcode, if the opcode is SExt. Still may
produce unsigned result.

Author: alexey-bataev

llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

@@ -15487,8 +15487,7 @@ void BoUpSLP::computeMinimumValueSizes() {
       TreeEntry *TE = VectorizableTree[Idx].get();
       if (MinBWs.contains(TE))
         continue;
-      bool IsSigned = TE->getOpcode() == Instruction::SExt ||
-                      any_of(TE->Scalars, [&](Value *R) {
+      bool IsSigned = any_of(TE->Scalars, [&](Value *R) {
                         return !isKnownNonNegative(R, SimplifyQuery(*DL));
                       });
       MinBWs.try_emplace(TE, MaxBitWidth, IsSigned);

llvm/test/Transforms/SLPVectorizer/AArch64/unsigned-after-sext-node.ll

@@ -4,10 +4,10 @@
 define i16 @test()  {
 ; CHECK-LABEL: define i16 @test() {
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[LNOT:%.*]] = xor i1 false, true
+; CHECK-NEXT:    [[LNOT:%.*]] = xor i1 true, true
 ; CHECK-NEXT:    [[LNOT_EXT:%.*]] = zext i1 [[LNOT]] to i16
 ; CHECK-NEXT:    [[ADD:%.*]] = add nsw i16 0, [[LNOT_EXT]]
-; CHECK-NEXT:    [[LNOT5:%.*]] = xor i1 false, true
+; CHECK-NEXT:    [[LNOT5:%.*]] = xor i1 true, true
 ; CHECK-NEXT:    [[LNOT_EXT6:%.*]] = zext i1 [[LNOT5]] to i16
 ; CHECK-NEXT:    [[ADD7:%.*]] = add nsw i16 [[ADD]], [[LNOT_EXT6]]
 ; CHECK-NEXT:    ret i16 [[ADD7]]