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[RISCV] Select Zvkb VANDN for shorter constant loading sequences (#123345)
This extends PR #120221 to vector instructions.
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+74
-37
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4 files changed

+74
-37
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‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

+18-1
Original file line numberDiff line numberDiff line change
@@ -3224,8 +3224,25 @@ bool RISCVDAGToDAGISel::selectInvLogicImm(SDValue N, SDValue &Val) {
32243224

32253225
// Abandon this transform if the constant is needed elsewhere.
32263226
for (const SDNode *U : N->users()) {
3227-
if (!ISD::isBitwiseLogicOp(U->getOpcode()))
3227+
switch (U->getOpcode()) {
3228+
case ISD::AND:
3229+
case ISD::OR:
3230+
case ISD::XOR:
3231+
if (!(Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()))
3232+
return false;
3233+
break;
3234+
case RISCVISD::VMV_V_X_VL:
3235+
if (!Subtarget->hasStdExtZvkb())
3236+
return false;
3237+
if (!all_of(U->users(), [](const SDNode *V) {
3238+
return V->getOpcode() == ISD::AND ||
3239+
V->getOpcode() == RISCVISD::AND_VL;
3240+
}))
3241+
return false;
3242+
break;
3243+
default:
32283244
return false;
3245+
}
32293246
}
32303247

32313248
// For 64-bit constants, the instruction sequences get complex,

‎llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

+21
Original file line numberDiff line numberDiff line change
@@ -624,6 +624,13 @@ foreach vti = AllIntegerVectors in {
624624
vti.RegClass:$rs2,
625625
vti.ScalarRegClass:$rs1,
626626
vti.AVL, vti.Log2SEW, TA_MA)>;
627+
def : Pat<(vti.Vector (and (riscv_splat_vector invLogicImm:$rs1),
628+
vti.RegClass:$rs2)),
629+
(!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX)
630+
(vti.Vector (IMPLICIT_DEF)),
631+
vti.RegClass:$rs2,
632+
invLogicImm:$rs1,
633+
vti.AVL, vti.Log2SEW, TA_MA)>;
627634
}
628635
}
629636

@@ -758,6 +765,20 @@ foreach vti = AllIntegerVectors in {
758765
GPR:$vl,
759766
vti.Log2SEW,
760767
TAIL_AGNOSTIC)>;
768+
769+
def : Pat<(vti.Vector (riscv_and_vl (riscv_splat_vector invLogicImm:$rs1),
770+
(vti.Vector vti.RegClass:$rs2),
771+
(vti.Vector vti.RegClass:$passthru),
772+
(vti.Mask V0),
773+
VLOpFrag)),
774+
(!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX#"_MASK")
775+
vti.RegClass:$passthru,
776+
vti.RegClass:$rs2,
777+
invLogicImm:$rs1,
778+
(vti.Mask V0),
779+
GPR:$vl,
780+
vti.Log2SEW,
781+
TAIL_AGNOSTIC)>;
761782
}
762783
}
763784

‎llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll

+28-26
Original file line numberDiff line numberDiff line change
@@ -1945,10 +1945,9 @@ define <vscale x 1 x i16> @vandn_vx_imm16(<vscale x 1 x i16> %x) {
19451945
;
19461946
; CHECK-ZVKB-LABEL: vandn_vx_imm16:
19471947
; CHECK-ZVKB: # %bb.0:
1948-
; CHECK-ZVKB-NEXT: lui a0, 8
1949-
; CHECK-ZVKB-NEXT: addi a0, a0, -1
1948+
; CHECK-ZVKB-NEXT: lui a0, 1048568
19501949
; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
1951-
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a0
1950+
; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0
19521951
; CHECK-ZVKB-NEXT: ret
19531952
%a = and <vscale x 1 x i16> splat (i16 32767), %x
19541953
ret <vscale x 1 x i16> %a
@@ -1965,10 +1964,9 @@ define <vscale x 1 x i16> @vandn_vx_swapped_imm16(<vscale x 1 x i16> %x) {
19651964
;
19661965
; CHECK-ZVKB-LABEL: vandn_vx_swapped_imm16:
19671966
; CHECK-ZVKB: # %bb.0:
1968-
; CHECK-ZVKB-NEXT: lui a0, 8
1969-
; CHECK-ZVKB-NEXT: addi a0, a0, -1
1967+
; CHECK-ZVKB-NEXT: lui a0, 1048568
19701968
; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
1971-
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a0
1969+
; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0
19721970
; CHECK-ZVKB-NEXT: ret
19731971
%a = and <vscale x 1 x i16> %x, splat (i16 32767)
19741972
ret <vscale x 1 x i16> %a
@@ -2018,11 +2016,10 @@ define <vscale x 1 x i64> @vandn_vx_imm64(<vscale x 1 x i64> %x) {
20182016
;
20192017
; CHECK-ZVKB64-LABEL: vandn_vx_imm64:
20202018
; CHECK-ZVKB64: # %bb.0:
2021-
; CHECK-ZVKB64-NEXT: li a0, -1
2022-
; CHECK-ZVKB64-NEXT: slli a0, a0, 56
2023-
; CHECK-ZVKB64-NEXT: addi a0, a0, 255
2019+
; CHECK-ZVKB64-NEXT: lui a0, 1048560
2020+
; CHECK-ZVKB64-NEXT: srli a0, a0, 8
20242021
; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
2025-
; CHECK-ZVKB64-NEXT: vand.vx v8, v8, a0
2022+
; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a0
20262023
; CHECK-ZVKB64-NEXT: ret
20272024
%a = and <vscale x 1 x i64> %x, splat (i64 -72057594037927681)
20282025
ret <vscale x 1 x i64> %a
@@ -2041,11 +2038,10 @@ define <vscale x 1 x i16> @vandn_vx_multi_imm16(<vscale x 1 x i16> %x, <vscale x
20412038
;
20422039
; CHECK-ZVKB-LABEL: vandn_vx_multi_imm16:
20432040
; CHECK-ZVKB: # %bb.0:
2044-
; CHECK-ZVKB-NEXT: lui a0, 4
2045-
; CHECK-ZVKB-NEXT: addi a0, a0, -1
2041+
; CHECK-ZVKB-NEXT: lui a0, 1048572
20462042
; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
2047-
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a0
2048-
; CHECK-ZVKB-NEXT: vand.vx v9, v9, a0
2043+
; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0
2044+
; CHECK-ZVKB-NEXT: vandn.vx v9, v9, a0
20492045
; CHECK-ZVKB-NEXT: vadd.vv v8, v8, v9
20502046
; CHECK-ZVKB-NEXT: ret
20512047
%a = and <vscale x 1 x i16> %x, splat (i16 16383)
@@ -2065,15 +2061,24 @@ define <vscale x 1 x i16> @vandn_vx_multi_scalar_imm16(<vscale x 1 x i16> %x, i1
20652061
; CHECK-NEXT: vadd.vx v8, v8, a0
20662062
; CHECK-NEXT: ret
20672063
;
2068-
; CHECK-ZVKB-LABEL: vandn_vx_multi_scalar_imm16:
2069-
; CHECK-ZVKB: # %bb.0:
2070-
; CHECK-ZVKB-NEXT: lui a1, 8
2071-
; CHECK-ZVKB-NEXT: addi a1, a1, -1
2072-
; CHECK-ZVKB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2073-
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a1
2074-
; CHECK-ZVKB-NEXT: or a0, a0, a1
2075-
; CHECK-ZVKB-NEXT: vadd.vx v8, v8, a0
2076-
; CHECK-ZVKB-NEXT: ret
2064+
; CHECK-ZVKB-NOZBB-LABEL: vandn_vx_multi_scalar_imm16:
2065+
; CHECK-ZVKB-NOZBB: # %bb.0:
2066+
; CHECK-ZVKB-NOZBB-NEXT: lui a1, 8
2067+
; CHECK-ZVKB-NOZBB-NEXT: addi a1, a1, -1
2068+
; CHECK-ZVKB-NOZBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2069+
; CHECK-ZVKB-NOZBB-NEXT: vand.vx v8, v8, a1
2070+
; CHECK-ZVKB-NOZBB-NEXT: or a0, a0, a1
2071+
; CHECK-ZVKB-NOZBB-NEXT: vadd.vx v8, v8, a0
2072+
; CHECK-ZVKB-NOZBB-NEXT: ret
2073+
;
2074+
; CHECK-ZVKB-ZBB-LABEL: vandn_vx_multi_scalar_imm16:
2075+
; CHECK-ZVKB-ZBB: # %bb.0:
2076+
; CHECK-ZVKB-ZBB-NEXT: lui a1, 1048568
2077+
; CHECK-ZVKB-ZBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2078+
; CHECK-ZVKB-ZBB-NEXT: vandn.vx v8, v8, a1
2079+
; CHECK-ZVKB-ZBB-NEXT: orn a0, a0, a1
2080+
; CHECK-ZVKB-ZBB-NEXT: vadd.vx v8, v8, a0
2081+
; CHECK-ZVKB-ZBB-NEXT: ret
20772082
%a = and <vscale x 1 x i16> %x, splat (i16 32767)
20782083
%b = or i16 %y, 32767
20792084
%head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
@@ -2104,6 +2109,3 @@ define <vscale x 1 x i16> @vand_vadd_vx_imm16(<vscale x 1 x i16> %x) {
21042109
%b = add <vscale x 1 x i16> %a, splat (i16 32767)
21052110
ret <vscale x 1 x i16> %b
21062111
}
2107-
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
2108-
; CHECK-ZVKB-NOZBB: {{.*}}
2109-
; CHECK-ZVKB-ZBB: {{.*}}

‎llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll

+7-10
Original file line numberDiff line numberDiff line change
@@ -1441,10 +1441,9 @@ define <vscale x 1 x i16> @vandn_vx_vp_imm16(<vscale x 1 x i16> %x, <vscale x 1
14411441
;
14421442
; CHECK-ZVKB-LABEL: vandn_vx_vp_imm16:
14431443
; CHECK-ZVKB: # %bb.0:
1444-
; CHECK-ZVKB-NEXT: lui a1, 8
1445-
; CHECK-ZVKB-NEXT: addi a1, a1, -1
1444+
; CHECK-ZVKB-NEXT: lui a1, 1048568
14461445
; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1447-
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a1, v0.t
1446+
; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a1, v0.t
14481447
; CHECK-ZVKB-NEXT: ret
14491448
%a = call <vscale x 1 x i16> @llvm.vp.and.nxv1i16(<vscale x 1 x i16> splat (i16 32767), <vscale x 1 x i16> %x, <vscale x 1 x i1> %mask, i32 %evl)
14501449
ret <vscale x 1 x i16> %a
@@ -1461,10 +1460,9 @@ define <vscale x 1 x i16> @vandn_vx_vp_swapped_imm16(<vscale x 1 x i16> %x, <vsc
14611460
;
14621461
; CHECK-ZVKB-LABEL: vandn_vx_vp_swapped_imm16:
14631462
; CHECK-ZVKB: # %bb.0:
1464-
; CHECK-ZVKB-NEXT: lui a1, 8
1465-
; CHECK-ZVKB-NEXT: addi a1, a1, -1
1463+
; CHECK-ZVKB-NEXT: lui a1, 1048568
14661464
; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1467-
; CHECK-ZVKB-NEXT: vand.vx v8, v8, a1, v0.t
1465+
; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a1, v0.t
14681466
; CHECK-ZVKB-NEXT: ret
14691467
%a = call <vscale x 1 x i16> @llvm.vp.and.nxv1i16(<vscale x 1 x i16> %x, <vscale x 1 x i16> splat (i16 32767), <vscale x 1 x i1> %mask, i32 %evl)
14701468
ret <vscale x 1 x i16> %a
@@ -1514,11 +1512,10 @@ define <vscale x 1 x i64> @vandn_vx_vp_imm64(<vscale x 1 x i64> %x, <vscale x 1
15141512
;
15151513
; CHECK-ZVKB64-LABEL: vandn_vx_vp_imm64:
15161514
; CHECK-ZVKB64: # %bb.0:
1517-
; CHECK-ZVKB64-NEXT: li a1, -1
1518-
; CHECK-ZVKB64-NEXT: slli a1, a1, 56
1519-
; CHECK-ZVKB64-NEXT: addi a1, a1, 255
1515+
; CHECK-ZVKB64-NEXT: lui a1, 1048560
1516+
; CHECK-ZVKB64-NEXT: srli a1, a1, 8
15201517
; CHECK-ZVKB64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1521-
; CHECK-ZVKB64-NEXT: vand.vx v8, v8, a1, v0.t
1518+
; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a1, v0.t
15221519
; CHECK-ZVKB64-NEXT: ret
15231520
%a = call <vscale x 1 x i64> @llvm.vp.and.nxv1i64(<vscale x 1 x i64> %x, <vscale x 1 x i64> splat (i64 -72057594037927681), <vscale x 1 x i1> %mask, i32 %evl)
15241521
ret <vscale x 1 x i64> %a

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