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[FMV][AArch64] Remove feature sha1 from FMV. (#108383)
Sha1 has been unified with sha2 in the ACLE spec (see ARM-software/acle#347) so I am changing the compiler to adhere to it.
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8 files changed

+13
-19
lines changed

8 files changed

+13
-19
lines changed

‎clang/test/CodeGen/aarch64-fmv-dependencies.c

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -111,9 +111,6 @@ __attribute__((target_version("rpres"))) int fmv(void) { return 0; }
111111
// CHECK: define dso_local i32 @fmv._Msb() #[[sb:[0-9]+]] {
112112
__attribute__((target_version("sb"))) int fmv(void) { return 0; }
113113

114-
// CHECK: define dso_local i32 @fmv._Msha1() #[[ATTR0:[0-9]+]] {
115-
__attribute__((target_version("sha1"))) int fmv(void) { return 0; }
116-
117114
// CHECK: define dso_local i32 @fmv._Msha2() #[[sha2:[0-9]+]] {
118115
__attribute__((target_version("sha2"))) int fmv(void) { return 0; }
119116

‎clang/test/CodeGen/attr-target-version.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ int foo() {
2424
return fmv()+fmv_one()+fmv_two();
2525
}
2626

27-
inline int __attribute__((target_version("sha1+pmull+f64mm"))) fmv_inline(void) { return 1; }
27+
inline int __attribute__((target_version("sha2+pmull+f64mm"))) fmv_inline(void) { return 1; }
2828
inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; }
2929
inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; }
3030
inline int __attribute__((target_version("dit+sve-ebf16"))) fmv_inline(void) { return 8; }
@@ -659,7 +659,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
659659
//
660660
//
661661
// CHECK: Function Attrs: noinline nounwind optnone
662-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf64mmMpmullMsha1
662+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf64mmMpmullMsha2
663663
// CHECK-SAME: () #[[ATTR23:[0-9]+]] {
664664
// CHECK-NEXT: entry:
665665
// CHECK-NEXT: ret i32 1
@@ -805,12 +805,12 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
805805
// CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-bitpermMsve2-pmull128
806806
// CHECK: resolver_else4:
807807
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
808-
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 34359773184
809-
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 34359773184
808+
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 34359775232
809+
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 34359775232
810810
// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
811811
// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
812812
// CHECK: resolver_return5:
813-
// CHECK-NEXT: ret ptr @fmv_inline._Mf64mmMpmullMsha1
813+
// CHECK-NEXT: ret ptr @fmv_inline._Mf64mmMpmullMsha2
814814
// CHECK: resolver_else6:
815815
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
816816
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 17246986240
@@ -1135,7 +1135,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
11351135
// CHECK: attributes #[[ATTR20]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+jsconv,+neon" }
11361136
// CHECK: attributes #[[ATTR21:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ls64" }
11371137
// CHECK: attributes #[[ATTR22]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sb" }
1138-
// CHECK: attributes #[[ATTR23]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+f64mm,+fp-armv8,+fullfp16,+neon,+sve" }
1138+
// CHECK: attributes #[[ATTR23]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+f64mm,+fp-armv8,+fullfp16,+neon,+sha2,+sve" }
11391139
// CHECK: attributes #[[ATTR24]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+fp-armv8,+fullfp16,+neon,+rdm,+sme" }
11401140
// CHECK: attributes #[[ATTR25]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+fp-armv8,+fullfp16,+i8mm,+neon,+sha2,+sha3,+sve" }
11411141
// CHECK: attributes #[[ATTR26]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+dit,+fp-armv8,+fullfp16,+neon,+sve" }

‎clang/test/Sema/attr-target-clones-aarch64.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -24,17 +24,17 @@ int __attribute__((target_clones("rng", "fp16fml+fp", "default"))) redecl4(void)
2424
// expected-error@+3 {{'target_clones' attribute does not match previous declaration}}
2525
// expected-note@-2 {{previous declaration is here}}
2626
// expected-warning@+1 {{version list contains entries that don't impact code generation}}
27-
int __attribute__((target_clones("dgh+memtag+rpres", "ebf16+dpb+sha1", "default"))) redecl4(void) { return 1; }
27+
int __attribute__((target_clones("dgh+memtag+rpres", "ebf16+dpb", "default"))) redecl4(void) { return 1; }
2828

2929
int __attribute__((target_version("flagm2"))) redef2(void) { return 1; }
3030
// expected-error@+2 {{multiversioned function redeclarations require identical target attributes}}
3131
// expected-note@-2 {{previous declaration is here}}
3232
int __attribute__((target_clones("flagm2", "default"))) redef2(void) { return 1; }
3333

34-
int __attribute__((target_clones("f32mm", "f64mm", "sha1+fp"))) redef3(void) { return 1; }
34+
int __attribute__((target_clones("f32mm", "f64mm", "sha2+fp"))) redef3(void) { return 1; }
3535
// expected-error@+2 {{'target_clones' attribute does not match previous declaration}}
3636
// expected-note@-2 {{previous declaration is here}}
37-
int __attribute__((target_clones("f32mm", "sha1+fp", "f64mm"))) redef3(void) { return 1; }
37+
int __attribute__((target_clones("f32mm", "sha2+fp", "f64mm"))) redef3(void) { return 1; }
3838

3939
int __attribute__((target_clones("rdm+lse+rdm", "lse+rdm"))) dup1(void) { return 1; }
4040
// expected-warning@+1 {{version list contains duplicate entries}}

‎clang/test/Sema/attr-target-version.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ void __attribute__((target_version("bti+flagm2"))) one(void) {}
3636
//expected-error@+1 {{multiversioned function redeclarations require identical target attributes}}
3737
void __attribute__((target_version("flagm2+bti"))) one(void) {}
3838

39-
void __attribute__((target_version("ssbs+sha1"))) two(void) {}
39+
void __attribute__((target_version("ssbs+sha2"))) two(void) {}
4040
void __attribute__((target_version("ssbs+fp16fml"))) two(void) {}
4141

4242
//expected-error@+1 {{'main' cannot be a multiversioned function}}
@@ -89,7 +89,7 @@ int bar() {
8989
return def();
9090
}
9191
// expected-error@+1 {{function declaration cannot become a multiversioned function after first usage}}
92-
int __attribute__((target_version("sha1"))) def(void) { return 1; }
92+
int __attribute__((target_version("sha2"))) def(void) { return 1; }
9393

9494
int __attribute__((target_version("sve"))) prot();
9595
// expected-error@-1 {{multiversioned function must have a prototype}}

‎compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ enum CPUFeatures {
3333
FEAT_FP,
3434
FEAT_SIMD,
3535
FEAT_CRC,
36-
FEAT_SHA1,
36+
RESERVED_FEAT_SHA1, // previously used and now ABI legacy
3737
FEAT_SHA2,
3838
FEAT_SHA3,
3939
FEAT_AES,

‎compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
3535
setCPUFeature(FEAT_RDM);
3636
if (hwcap & HWCAP_AES)
3737
setCPUFeature(FEAT_AES);
38-
if (hwcap & HWCAP_SHA1)
39-
setCPUFeature(FEAT_SHA1);
4038
if (hwcap & HWCAP_SHA2)
4139
setCPUFeature(FEAT_SHA2);
4240
if (hwcap & HWCAP_JSCVT)

‎llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ enum CPUFeatures {
3333
FEAT_FP,
3434
FEAT_SIMD,
3535
FEAT_CRC,
36-
FEAT_SHA1,
36+
RESERVED_FEAT_SHA1, // previously used and now ABI legacy
3737
FEAT_SHA2,
3838
FEAT_SHA3,
3939
FEAT_AES,

‎llvm/lib/Target/AArch64/AArch64FMV.td

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,6 @@ def : FMVExtension<"rdm", "FEAT_RDM", "+rdm,+fp-armv8,+neon", 108>;
7373
def : FMVExtension<"rng", "FEAT_RNG", "+rand", 10>;
7474
def : FMVExtension<"rpres", "FEAT_RPRES", "", 300>;
7575
def : FMVExtension<"sb", "FEAT_SB", "+sb", 470>;
76-
def : FMVExtension<"sha1", "FEAT_SHA1", "+fp-armv8,+neon", 120>;
7776
def : FMVExtension<"sha2", "FEAT_SHA2", "+sha2,+fp-armv8,+neon", 130>;
7877
def : FMVExtension<"sha3", "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>;
7978
def : FMVExtension<"simd", "FEAT_SIMD", "+fp-armv8,+neon", 100>;

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