fixup! use ConstantInt to represent G_VSCALE operand

Author: michaelmaitland

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

@@ -1150,11 +1150,21 @@ class MachineIRBuilder {
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre \p Res must be a generic virtual register with scalar type.
-  /// \pre \p Src must be a generic virtual register with scalar type.
   ///
   /// \return a MachineInstrBuilder for the newly created instruction.
   MachineInstrBuilder buildVScale(const DstOp &Res, unsigned MinElts);
 
+  /// Build and insert \p Res = G_VSCALE \p MinElts
+  ///
+  /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
+  /// into \p Res.
+  ///
+  /// \pre setBasicBlock or setMI must have been called.
+  /// \pre \p Res must be a generic virtual register with scalar type.
+  ///
+  /// \return a MachineInstrBuilder for the newly created instruction.
+  MachineInstrBuilder buildVScale(const DstOp &Res, const ConstantInt &MinElts);
+
   /// Build and insert a G_INTRINSIC instruction.
   ///
   /// There are four different opcodes based on combinations of whether the

llvm/include/llvm/Target/GenericOpcodes.td

@@ -1294,7 +1294,7 @@ def G_MERGE_VALUES : GenericInstruction {
 // operand into the destination register.
 def G_VSCALE : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins untyped_imm_0:$src);
+  let InOperandList = (ins unknown:$src);
   let hasSideEffects = false;
 }
 

llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

@@ -795,7 +795,20 @@ MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res,
 
 MachineInstrBuilder MachineIRBuilder::buildVScale(const DstOp &Res,
                                                   unsigned MinElts) {
-  return buildInstr(TargetOpcode::G_VSCALE, {Res}, {uint64_t(MinElts)});
+
+  auto IntN = IntegerType::get(getMF().getFunction().getContext(),
+                               Res.getLLTTy(*getMRI()).getScalarSizeInBits());
+  ConstantInt *CI = ConstantInt::get(IntN, MinElts);
+  return buildVScale(Res, *CI);
+}
+
+MachineInstrBuilder MachineIRBuilder::buildVScale(const DstOp &Res,
+                                                  const ConstantInt &MinElts) {
+  auto VScale = buildInstr(TargetOpcode::G_VSCALE);
+  VScale->setDebugLoc(DebugLoc());
+  Res.addDefToMIB(*getMRI(), VScale);
+  VScale.addCImm(&MinElts);
+  return VScale;
 }
 
 static unsigned getIntrinsicOpcode(bool HasSideEffects, bool IsConvergent) {

llvm/lib/CodeGen/MachineVerifier.cpp

@@ -1614,11 +1614,11 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
     break;
   }
   case TargetOpcode::G_VSCALE: {
-    if (!MI->getOperand(1).isImm()) {
-      report("G_VSCALE operand #1 must be an immediate", MI);
+    if (!MI->getOperand(1).isCImm()) {
+      report("G_VSCALE operand must be cimm", MI);
       break;
     }
-    if (MI->getOperand(1).getImm() == 0) {
+    if (MI->getOperand(1).getCImm()->isZero()) {
       report("G_VSCALE immediate cannot be zero", MI);
       break;
     }

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

@@ -616,7 +616,7 @@
 # DEBUG-NEXT: G_BRJT (opcode {{[0-9]+}}): 2 type indices
 # DEBUG-NEXT: .. the first uncovered type index: 2, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
-# DEBUG-NEXT: G_VSCALE (opcode {{[0-9]+}}): 1 type index, 1 imm index
+# DEBUG-NEXT: G_VSCALE (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_INSERT_SUBVECTOR (opcode {{[0-9]+}}): 2 type indices, 1 imm index

llvm/test/MachineVerifier/test_g_vscale.mir

@@ -7,7 +7,7 @@ body: |
 
   %1:_(s32) = G_CONSTANT 4
 
-  ; CHECK: G_VSCALE operand #1 must be an immediate
+  ; CHECK: G_VSCALE operand must be cimm
   %2:_(s32) = G_VSCALE %1
 
   ; CHECK: G_VSCALE immediate cannot be zero