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[InstSimplify] Fix incorrect poison propagation when folding phi (#96631)
We can only replace phi(X, undef) with X, if X is known not to be poison. Otherwise, the result may be more poisonous on the undef branch. Fixes #68683.
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12 files changed

+46
-34
lines changed

12 files changed

+46
-34
lines changed

‎llvm/lib/Analysis/InstructionSimplify.cpp

+8-1
Original file line numberDiff line numberDiff line change
@@ -5315,7 +5315,14 @@ static Value *simplifyPHINode(PHINode *PN, ArrayRef<Value *> IncomingValues,
53155315
// If we have a PHI node like phi(X, undef, X), where X is defined by some
53165316
// instruction, we cannot return X as the result of the PHI node unless it
53175317
// dominates the PHI block.
5318-
return valueDominatesPHI(CommonValue, PN, Q.DT) ? CommonValue : nullptr;
5318+
if (!valueDominatesPHI(CommonValue, PN, Q.DT))
5319+
return nullptr;
5320+
5321+
// Make sure we do not replace an undef value with poison.
5322+
if (HasUndefInput &&
5323+
!isGuaranteedNotToBePoison(CommonValue, Q.AC, Q.CxtI, Q.DT))
5324+
return nullptr;
5325+
return CommonValue;
53195326
}
53205327

53215328
return CommonValue;

‎llvm/test/CodeGen/AArch64/convertphitype.ll

+3-2
Original file line numberDiff line numberDiff line change
@@ -341,6 +341,7 @@ define float @convphi_loopdelayed(ptr %s, ptr %d, i64 %n) {
341341
; CHECK-NEXT: entry:
342342
; CHECK-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[N:%.*]], 0
343343
; CHECK-NEXT: [[LS:%.*]] = load i32, ptr [[S:%.*]], align 4
344+
; CHECK-NEXT: [[LS_BC:%.*]] = bitcast i32 [[LS]] to float
344345
; CHECK-NEXT: br i1 [[CMP15]], label [[LOOP:%.*]], label [[END:%.*]]
345346
; CHECK: loop:
346347
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
@@ -349,8 +350,8 @@ define float @convphi_loopdelayed(ptr %s, ptr %d, i64 %n) {
349350
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
350351
; CHECK-NEXT: br i1 [[EXITCOND]], label [[END]], label [[LOOP]]
351352
; CHECK: end:
352-
; CHECK-NEXT: [[B:%.*]] = bitcast i32 [[LS]] to float
353-
; CHECK-NEXT: ret float [[B]]
353+
; CHECK-NEXT: [[PHI_TC:%.*]] = phi float [ undef, [[ENTRY]] ], [ [[LS_BC]], [[LOOP]] ]
354+
; CHECK-NEXT: ret float [[PHI_TC]]
354355
;
355356
entry:
356357
%cmp15 = icmp sgt i64 %n, 0

‎llvm/test/CodeGen/AArch64/sve-breakdown-scalable-vectortype.ll

+21-21
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ define <vscale x 32 x i8> @wide_32i8(i1 %b, <vscale x 16 x i8> %legal, <vscale x
3333
br i1 %b, label %L1, label %L2
3434
L1:
3535
call aarch64_sve_vector_pcs void @bar()
36-
ret <vscale x 32 x i8> undef
36+
ret <vscale x 32 x i8> poison
3737
L2:
3838
ret <vscale x 32 x i8> %illegal
3939
}
@@ -61,7 +61,7 @@ define <vscale x 16 x i16> @wide_16i16(i1 %b, <vscale x 16 x i8> %legal, <vscale
6161
br i1 %b, label %L1, label %L2
6262
L1:
6363
call aarch64_sve_vector_pcs void @bar()
64-
ret <vscale x 16 x i16> undef
64+
ret <vscale x 16 x i16> poison
6565
L2:
6666
ret <vscale x 16 x i16> %illegal
6767
}
@@ -89,7 +89,7 @@ define <vscale x 8 x i32> @wide_8i32(i1 %b, <vscale x 16 x i8> %legal, <vscale x
8989
br i1 %b, label %L1, label %L2
9090
L1:
9191
call aarch64_sve_vector_pcs void @bar()
92-
ret <vscale x 8 x i32> undef
92+
ret <vscale x 8 x i32> poison
9393
L2:
9494
ret <vscale x 8 x i32> %illegal
9595
}
@@ -117,7 +117,7 @@ define <vscale x 4 x i64> @wide_4i64(i1 %b, <vscale x 16 x i8> %legal, <vscale x
117117
br i1 %b, label %L1, label %L2
118118
L1:
119119
call aarch64_sve_vector_pcs void @bar()
120-
ret <vscale x 4 x i64> undef
120+
ret <vscale x 4 x i64> poison
121121
L2:
122122
ret <vscale x 4 x i64> %illegal
123123
}
@@ -145,7 +145,7 @@ define <vscale x 16 x half> @wide_16f16(i1 %b, <vscale x 16 x i8> %legal, <vscal
145145
br i1 %b, label %L1, label %L2
146146
L1:
147147
call aarch64_sve_vector_pcs void @bar()
148-
ret <vscale x 16 x half> undef
148+
ret <vscale x 16 x half> poison
149149
L2:
150150
ret <vscale x 16 x half> %illegal
151151
}
@@ -173,7 +173,7 @@ define <vscale x 8 x float> @wide_8f32(i1 %b, <vscale x 16 x i8> %legal, <vscale
173173
br i1 %b, label %L1, label %L2
174174
L1:
175175
call aarch64_sve_vector_pcs void @bar()
176-
ret <vscale x 8 x float> undef
176+
ret <vscale x 8 x float> poison
177177
L2:
178178
ret <vscale x 8 x float> %illegal
179179
}
@@ -201,7 +201,7 @@ define <vscale x 4 x double> @wide_4f64(i1 %b, <vscale x 16 x i8> %legal, <vscal
201201
br i1 %b, label %L1, label %L2
202202
L1:
203203
call aarch64_sve_vector_pcs void @bar()
204-
ret <vscale x 4 x double> undef
204+
ret <vscale x 4 x double> poison
205205
L2:
206206
ret <vscale x 4 x double> %illegal
207207
}
@@ -237,7 +237,7 @@ define <vscale x 48 x i8> @wide_48i8(i1 %b, <vscale x 16 x i8> %legal, <vscale x
237237
br i1 %b, label %L1, label %L2
238238
L1:
239239
call aarch64_sve_vector_pcs void @bar()
240-
ret <vscale x 48 x i8> undef
240+
ret <vscale x 48 x i8> poison
241241
L2:
242242
ret <vscale x 48 x i8> %illegal
243243
}
@@ -269,7 +269,7 @@ define <vscale x 24 x i16> @wide_24i16(i1 %b, <vscale x 16 x i8> %legal, <vscale
269269
br i1 %b, label %L1, label %L2
270270
L1:
271271
call aarch64_sve_vector_pcs void @bar()
272-
ret <vscale x 24 x i16> undef
272+
ret <vscale x 24 x i16> poison
273273
L2:
274274
ret <vscale x 24 x i16> %illegal
275275
}
@@ -301,7 +301,7 @@ define <vscale x 12 x i32> @wide_12i32(i1 %b, <vscale x 16 x i8> %legal, <vscale
301301
br i1 %b, label %L1, label %L2
302302
L1:
303303
call aarch64_sve_vector_pcs void @bar()
304-
ret <vscale x 12 x i32> undef
304+
ret <vscale x 12 x i32> poison
305305
L2:
306306
ret <vscale x 12 x i32> %illegal
307307
}
@@ -333,7 +333,7 @@ define <vscale x 6 x i64> @wide_6i64(i1 %b, <vscale x 16 x i8> %legal, <vscale x
333333
br i1 %b, label %L1, label %L2
334334
L1:
335335
call aarch64_sve_vector_pcs void @bar()
336-
ret <vscale x 6 x i64> undef
336+
ret <vscale x 6 x i64> poison
337337
L2:
338338
ret <vscale x 6 x i64> %illegal
339339
}
@@ -365,7 +365,7 @@ define <vscale x 24 x half> @wide_24f16(i1 %b, <vscale x 16 x i8> %legal, <vscal
365365
br i1 %b, label %L1, label %L2
366366
L1:
367367
call aarch64_sve_vector_pcs void @bar()
368-
ret <vscale x 24 x half> undef
368+
ret <vscale x 24 x half> poison
369369
L2:
370370
ret <vscale x 24 x half> %illegal
371371
}
@@ -397,7 +397,7 @@ define <vscale x 12 x float> @wide_12f32(i1 %b, <vscale x 16 x i8> %legal, <vsca
397397
br i1 %b, label %L1, label %L2
398398
L1:
399399
call aarch64_sve_vector_pcs void @bar()
400-
ret <vscale x 12 x float> undef
400+
ret <vscale x 12 x float> poison
401401
L2:
402402
ret <vscale x 12 x float> %illegal
403403
}
@@ -429,7 +429,7 @@ define <vscale x 6 x double> @wide_6f64(i1 %b, <vscale x 16 x i8> %legal, <vscal
429429
br i1 %b, label %L1, label %L2
430430
L1:
431431
call aarch64_sve_vector_pcs void @bar()
432-
ret <vscale x 6 x double> undef
432+
ret <vscale x 6 x double> poison
433433
L2:
434434
ret <vscale x 6 x double> %illegal
435435
}
@@ -469,7 +469,7 @@ define <vscale x 64 x i8> @wide_64i8(i1 %b, <vscale x 16 x i8> %legal, <vscale x
469469
br i1 %b, label %L1, label %L2
470470
L1:
471471
call aarch64_sve_vector_pcs void @bar()
472-
ret <vscale x 64 x i8> undef
472+
ret <vscale x 64 x i8> poison
473473
L2:
474474
ret <vscale x 64 x i8> %illegal
475475
}
@@ -505,7 +505,7 @@ define <vscale x 32 x i16> @wide_32i16(i1 %b, <vscale x 16 x i8> %legal, <vscale
505505
br i1 %b, label %L1, label %L2
506506
L1:
507507
call aarch64_sve_vector_pcs void @bar()
508-
ret <vscale x 32 x i16> undef
508+
ret <vscale x 32 x i16> poison
509509
L2:
510510
ret <vscale x 32 x i16> %illegal
511511
}
@@ -541,7 +541,7 @@ define <vscale x 16 x i32> @wide_16i32(i1 %b, <vscale x 16 x i8> %legal, <vscale
541541
br i1 %b, label %L1, label %L2
542542
L1:
543543
call aarch64_sve_vector_pcs void @bar()
544-
ret <vscale x 16 x i32> undef
544+
ret <vscale x 16 x i32> poison
545545
L2:
546546
ret <vscale x 16 x i32> %illegal
547547
}
@@ -577,7 +577,7 @@ define <vscale x 8 x i64> @wide_8i64(i1 %b, <vscale x 16 x i8> %legal, <vscale x
577577
br i1 %b, label %L1, label %L2
578578
L1:
579579
call aarch64_sve_vector_pcs void @bar()
580-
ret <vscale x 8 x i64> undef
580+
ret <vscale x 8 x i64> poison
581581
L2:
582582
ret <vscale x 8 x i64> %illegal
583583
}
@@ -613,7 +613,7 @@ define <vscale x 32 x half> @wide_32f16(i1 %b, <vscale x 16 x i8> %legal, <vscal
613613
br i1 %b, label %L1, label %L2
614614
L1:
615615
call aarch64_sve_vector_pcs void @bar()
616-
ret <vscale x 32 x half> undef
616+
ret <vscale x 32 x half> poison
617617
L2:
618618
ret <vscale x 32 x half> %illegal
619619
}
@@ -649,7 +649,7 @@ define <vscale x 16 x float> @wide_16f32(i1 %b, <vscale x 16 x i8> %legal, <vsca
649649
br i1 %b, label %L1, label %L2
650650
L1:
651651
call aarch64_sve_vector_pcs void @bar()
652-
ret <vscale x 16 x float> undef
652+
ret <vscale x 16 x float> poison
653653
L2:
654654
ret <vscale x 16 x float> %illegal
655655
}
@@ -685,7 +685,7 @@ define <vscale x 8 x double> @wide_8f64(i1 %b, <vscale x 16 x i8> %legal, <vscal
685685
br i1 %b, label %L1, label %L2
686686
L1:
687687
call aarch64_sve_vector_pcs void @bar()
688-
ret <vscale x 8 x double> undef
688+
ret <vscale x 8 x double> poison
689689
L2:
690690
ret <vscale x 8 x double> %illegal
691691
}

‎llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ for.body: ; preds = %for.body, %entry
3434
%optr.0102 = phi ptr [ %incdec.ptr24.3, %for.body ], [ %p3, %entry ]
3535
%iptr4.0101 = phi ptr [ %incdec.ptr23.3, %for.body ], [ %incdec.ptr18, %entry ]
3636
%iptr3.0100 = phi ptr [ %incdec.ptr22.3, %for.body ], [ %incdec.ptr17, %entry ]
37-
%iptr2.099 = phi ptr [ undef, %for.body ], [ %incdec.ptr16, %entry ]
37+
%iptr2.099 = phi ptr [ poison, %for.body ], [ %incdec.ptr16, %entry ]
3838
%iptr1.098 = phi ptr [ %incdec.ptr20.3, %for.body ], [ %incdec.ptr15, %entry ]
3939
%iptr0.097 = phi ptr [ %incdec.ptr19.3, %for.body ], [ %incdec.ptr, %entry ]
4040
%dVsumv1.096 = phi <32 x i32> [ %60, %for.body ], [ undef, %entry ]

‎llvm/test/CodeGen/Hexagon/trunc-mpy.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ b1: ; preds = %b0
6969

7070
b2: ; preds = %b2, %b1
7171
%v2 = phi ptr [ %v0, %b1 ], [ %v14, %b2 ]
72-
%v3 = phi ptr [ %v1, %b1 ], [ undef, %b2 ]
72+
%v3 = phi ptr [ %v1, %b1 ], [ poison, %b2 ]
7373
%v4 = phi ptr [ null, %b1 ], [ %v6, %b2 ]
7474
%v5 = load i32, ptr %v4, align 4
7575
%v6 = getelementptr inbounds i32, ptr %v4, i32 2

‎llvm/test/CodeGen/PowerPC/sms-phi-5.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ define void @phi5() unnamed_addr {
3535
%4 = phi i16 [ %18, %3 ], [ undef, %1 ]
3636
%5 = phi i16 [ %13, %3 ], [ undef, %1 ]
3737
%6 = phi i16 [ %11, %3 ], [ undef, %1 ]
38-
%7 = phi i16 [ undef, %3 ], [ %2, %1 ]
38+
%7 = phi i16 [ poison, %3 ], [ %2, %1 ]
3939
%8 = phi i32 [ %19, %3 ], [ undef, %1 ]
4040
%9 = lshr i16 %6, 1
4141
%10 = shl i16 %7, 15

‎llvm/test/Transforms/InstCombine/phi.ll

+2-1
Original file line numberDiff line numberDiff line change
@@ -93,9 +93,10 @@ define i32 @test5_undef(i32 %A, i1 %cond) {
9393
; CHECK-NEXT: BB0:
9494
; CHECK-NEXT: br label [[LOOP:%.*]]
9595
; CHECK: Loop:
96+
; CHECK-NEXT: [[B:%.*]] = phi i32 [ [[A:%.*]], [[BB0:%.*]] ], [ undef, [[LOOP]] ]
9697
; CHECK-NEXT: br i1 [[COND:%.*]], label [[LOOP]], label [[EXIT:%.*]]
9798
; CHECK: Exit:
98-
; CHECK-NEXT: ret i32 [[A:%.*]]
99+
; CHECK-NEXT: ret i32 [[B]]
99100
;
100101
BB0:
101102
br label %Loop

‎llvm/test/Transforms/InstSimplify/phi.ll

+2-1
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,8 @@ define i32 @undef(i1 %cond, i32 %v) {
8181
; CHECK: B:
8282
; CHECK-NEXT: br label [[EXIT]]
8383
; CHECK: EXIT:
84-
; CHECK-NEXT: ret i32 [[V:%.*]]
84+
; CHECK-NEXT: [[W:%.*]] = phi i32 [ [[V:%.*]], [[A]] ], [ undef, [[B]] ]
85+
; CHECK-NEXT: ret i32 [[W]]
8586
;
8687
br i1 %cond, label %A, label %B
8788
A:

‎llvm/test/Transforms/LoopDeletion/pr53969.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ define void @test() {
4444
; CHECK-NEXT: br i1 false, label [[BB11]], label [[BB12:%.*]]
4545
; CHECK: bb42:
4646
; CHECK-NEXT: [[TMP24_LCSSA:%.*]] = phi i32 [ undef, [[BB22]] ]
47-
; CHECK-NEXT: [[TMP18_LCSSA4:%.*]] = phi i64 [ 0, [[BB22]] ]
47+
; CHECK-NEXT: [[TMP18_LCSSA4:%.*]] = phi i64 [ undef, [[BB22]] ]
4848
; CHECK-NEXT: store atomic i64 [[TMP18_LCSSA4]], ptr addrspace(1) undef unordered, align 8
4949
; CHECK-NEXT: call void @use(i32 [[TMP24_LCSSA]])
5050
; CHECK-NEXT: ret void

‎llvm/test/Transforms/LoopVectorize/pr31190.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
; is a SCEV AddRec with respect to an outer loop.
66

77
; In this case, the problematic PHI is:
8-
; %0 = phi i32 [ undef, %for.cond1.preheader ], [ %inc54, %for.body3 ]
8+
; %0 = phi i32 [ poison, %for.cond1.preheader ], [ %inc54, %for.body3 ]
99
; Since %inc54 is the IV of the outer loop, and %0 equivalent to it,
1010
; we get the situation described above.
1111

@@ -47,7 +47,7 @@ for.cond1.preheader: ; preds = %for.cond1.for.inc4_
4747

4848
for.body3: ; preds = %for.body3, %for.cond1.preheader
4949
%inc1 = phi i32 [ %inc.lcssa3, %for.cond1.preheader ], [ %inc, %for.body3 ]
50-
%0 = phi i32 [ undef, %for.cond1.preheader ], [ %inc54, %for.body3 ]
50+
%0 = phi i32 [ poison, %for.cond1.preheader ], [ %inc54, %for.body3 ]
5151
%idxprom = sext i32 %0 to i64
5252
%arrayidx = getelementptr inbounds [1 x i32], ptr @b, i64 0, i64 %idxprom
5353
store i32 4, ptr %arrayidx, align 4

‎llvm/test/Transforms/Mem2Reg/UndefValuesMerge.ll

+2-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,8 @@ define i32 @testfunc(i1 %C, i32 %i, i8 %j) {
88
; CHECK: [[T]]:
99
; CHECK-NEXT: br label %[[CONT]]
1010
; CHECK: [[CONT]]:
11-
; CHECK-NEXT: ret i32 [[I]]
11+
; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ [[I]], %[[T]] ], [ undef, [[TMP0:%.*]] ]
12+
; CHECK-NEXT: ret i32 [[I_0]]
1213
;
1314
%I = alloca i32
1415
br i1 %C, label %T, label %Cont

‎llvm/test/Transforms/Mem2Reg/single-store.ll

+2-1
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,8 @@ define i8 @single_store_maybe_poison(i1 %cond, i8 %x) {
3030
; CHECK: [[IF]]:
3131
; CHECK-NEXT: br label %[[EXIT]]
3232
; CHECK: [[EXIT]]:
33-
; CHECK-NEXT: ret i8 [[X]]
33+
; CHECK-NEXT: [[A_0:%.*]] = phi i8 [ [[X]], %[[IF]] ], [ undef, [[TMP0:%.*]] ]
34+
; CHECK-NEXT: ret i8 [[A_0]]
3435
;
3536
%a = alloca i8, align 1
3637
br i1 %cond, label %if, label %exit

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