@@ -18032,7 +18032,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
18032
18032
}
18033
18033
18034
18034
// Allocate to a register if possible, or else a stack slot.
18035
- Register Reg = MCRegister() ;
18035
+ Register Reg;
18036
18036
unsigned StoreSizeBytes = XLen / 8;
18037
18037
Align StackAlign = Align(XLen / 8);
18038
18038
@@ -18129,7 +18129,7 @@ void RISCVTargetLowering::analyzeInputArgs(
18129
18129
unsigned NumArgs = Ins.size();
18130
18130
FunctionType *FType = MF.getFunction().getFunctionType();
18131
18131
18132
- std::vector <Type *> TypeList;
18132
+ SmallVector <Type *, 4 > TypeList;
18133
18133
if (IsRet)
18134
18134
TypeList.push_back(MF.getFunction().getReturnType());
18135
18135
else
@@ -18164,7 +18164,7 @@ void RISCVTargetLowering::analyzeOutputArgs(
18164
18164
CallLoweringInfo *CLI, RISCVCCAssignFn Fn) const {
18165
18165
unsigned NumArgs = Outs.size();
18166
18166
18167
- std::vector <Type *> TypeList;
18167
+ SmallVector <Type *, 4 > TypeList;
18168
18168
if (IsRet)
18169
18169
TypeList.push_back(MF.getFunction().getReturnType());
18170
18170
else if (CLI)
@@ -19073,8 +19073,7 @@ bool RISCVTargetLowering::CanLowerReturn(
19073
19073
SmallVector<CCValAssign, 16> RVLocs;
19074
19074
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
19075
19075
19076
- std::vector<Type *> TypeList = {MF.getFunction().getReturnType()};
19077
- RVVArgDispatcher Dispatcher{&MF, this, TypeList};
19076
+ RVVArgDispatcher Dispatcher{&MF, this, MF.getFunction().getReturnType()};
19078
19077
19079
19078
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
19080
19079
MVT VT = Outs[i].VT;
@@ -20877,7 +20876,7 @@ unsigned RISCVTargetLowering::getMinimumJumpTableEntries() const {
20877
20876
return Subtarget.getMinimumJumpTableEntries();
20878
20877
}
20879
20878
20880
- void RVVArgDispatcher::constructArgInfos(Type *Ty) {
20879
+ void RVVArgDispatcher::constructArgInfos(Type *Ty, bool &FirstMaskAssigned ) {
20881
20880
const DataLayout &DL = MF->getDataLayout();
20882
20881
const Function &F = MF->getFunction();
20883
20882
LLVMContext &Context = F.getContext();
@@ -20909,21 +20908,23 @@ void RVVArgDispatcher::constructArgInfos(Type *Ty) {
20909
20908
if (RegisterVT.isFixedLengthVector())
20910
20909
RegisterVT = TLI->getContainerForFixedLengthVector(RegisterVT);
20911
20910
20912
- RVVArgInfo Info{1, RegisterVT, false};
20913
- RVVArgInfos.insert(RVVArgInfos.end(), NumRegs, Info);
20911
+ if (!FirstMaskAssigned && RegisterVT.getVectorElementType() == MVT::i1) {
20912
+ RVVArgInfos.push_back({1, RegisterVT, true});
20913
+ FirstMaskAssigned = true;
20914
+ } else {
20915
+ RVVArgInfos.push_back({1, RegisterVT, false});
20916
+ }
20917
+
20918
+ RVVArgInfos.insert(RVVArgInfos.end(), --NumRegs, {1, RegisterVT, false});
20914
20919
}
20915
20920
}
20916
20921
}
20917
20922
20918
- void RVVArgDispatcher::construct(const std::vector<Type *> &TypeList) {
20923
+ void RVVArgDispatcher::constructArgInfos(
20924
+ const SmallVectorImpl<Type *> &TypeList) {
20925
+ bool FirstVMaskAssigned = false;
20919
20926
for (Type *Ty : TypeList)
20920
- constructArgInfos(Ty);
20921
-
20922
- for (auto &Info : RVVArgInfos)
20923
- if (Info.NF == 1 && Info.VT.getVectorElementType() == MVT::i1) {
20924
- Info.FirstVMask = true;
20925
- break;
20926
- }
20927
+ constructArgInfos(Ty, FirstVMaskAssigned);
20927
20928
}
20928
20929
20929
20930
void RVVArgDispatcher::allocatePhysReg(unsigned NF, unsigned LMul,
0 commit comments