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fixup! [RISCV] RISCV vector calling convention (2/2)
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3 files changed

+27
-26
lines changed

3 files changed

+27
-26
lines changed

llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -521,7 +521,7 @@ bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
521521
CallingConv::ID CC = F.getCallingConv();
522522

523523
SmallVector<ArgInfo, 32> SplitArgInfos;
524-
std::vector<Type *> TypeList;
524+
SmallVector<Type *, 4> TypeList;
525525
unsigned Index = 0;
526526
for (auto &Arg : F.args()) {
527527
// Construct the ArgInfo object from destination register and argument type.
@@ -579,7 +579,7 @@ bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
579579

580580
SmallVector<ArgInfo, 32> SplitArgInfos;
581581
SmallVector<ISD::OutputArg, 8> Outs;
582-
std::vector<Type *> TypeList;
582+
SmallVector<Type *, 4> TypeList;
583583
for (auto &AInfo : Info.OrigArgs) {
584584
// Handle any required unmerging of split value types from a given VReg into
585585
// physical registers. ArgInfo objects are constructed correspondingly and

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 17 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -18032,7 +18032,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
1803218032
}
1803318033

1803418034
// Allocate to a register if possible, or else a stack slot.
18035-
Register Reg = MCRegister();
18035+
Register Reg;
1803618036
unsigned StoreSizeBytes = XLen / 8;
1803718037
Align StackAlign = Align(XLen / 8);
1803818038

@@ -18129,7 +18129,7 @@ void RISCVTargetLowering::analyzeInputArgs(
1812918129
unsigned NumArgs = Ins.size();
1813018130
FunctionType *FType = MF.getFunction().getFunctionType();
1813118131

18132-
std::vector<Type *> TypeList;
18132+
SmallVector<Type *, 4> TypeList;
1813318133
if (IsRet)
1813418134
TypeList.push_back(MF.getFunction().getReturnType());
1813518135
else
@@ -18164,7 +18164,7 @@ void RISCVTargetLowering::analyzeOutputArgs(
1816418164
CallLoweringInfo *CLI, RISCVCCAssignFn Fn) const {
1816518165
unsigned NumArgs = Outs.size();
1816618166

18167-
std::vector<Type *> TypeList;
18167+
SmallVector<Type *, 4> TypeList;
1816818168
if (IsRet)
1816918169
TypeList.push_back(MF.getFunction().getReturnType());
1817018170
else if (CLI)
@@ -19073,8 +19073,7 @@ bool RISCVTargetLowering::CanLowerReturn(
1907319073
SmallVector<CCValAssign, 16> RVLocs;
1907419074
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
1907519075

19076-
std::vector<Type *> TypeList = {MF.getFunction().getReturnType()};
19077-
RVVArgDispatcher Dispatcher{&MF, this, TypeList};
19076+
RVVArgDispatcher Dispatcher{&MF, this, MF.getFunction().getReturnType()};
1907819077

1907919078
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
1908019079
MVT VT = Outs[i].VT;
@@ -20877,7 +20876,7 @@ unsigned RISCVTargetLowering::getMinimumJumpTableEntries() const {
2087720876
return Subtarget.getMinimumJumpTableEntries();
2087820877
}
2087920878

20880-
void RVVArgDispatcher::constructArgInfos(Type *Ty) {
20879+
void RVVArgDispatcher::constructArgInfos(Type *Ty, bool &FirstMaskAssigned) {
2088120880
const DataLayout &DL = MF->getDataLayout();
2088220881
const Function &F = MF->getFunction();
2088320882
LLVMContext &Context = F.getContext();
@@ -20909,21 +20908,23 @@ void RVVArgDispatcher::constructArgInfos(Type *Ty) {
2090920908
if (RegisterVT.isFixedLengthVector())
2091020909
RegisterVT = TLI->getContainerForFixedLengthVector(RegisterVT);
2091120910

20912-
RVVArgInfo Info{1, RegisterVT, false};
20913-
RVVArgInfos.insert(RVVArgInfos.end(), NumRegs, Info);
20911+
if (!FirstMaskAssigned && RegisterVT.getVectorElementType() == MVT::i1) {
20912+
RVVArgInfos.push_back({1, RegisterVT, true});
20913+
FirstMaskAssigned = true;
20914+
} else {
20915+
RVVArgInfos.push_back({1, RegisterVT, false});
20916+
}
20917+
20918+
RVVArgInfos.insert(RVVArgInfos.end(), --NumRegs, {1, RegisterVT, false});
2091420919
}
2091520920
}
2091620921
}
2091720922

20918-
void RVVArgDispatcher::construct(const std::vector<Type *> &TypeList) {
20923+
void RVVArgDispatcher::constructArgInfos(
20924+
const SmallVectorImpl<Type *> &TypeList) {
20925+
bool FirstVMaskAssigned = false;
2091920926
for (Type *Ty : TypeList)
20920-
constructArgInfos(Ty);
20921-
20922-
for (auto &Info : RVVArgInfos)
20923-
if (Info.NF == 1 && Info.VT.getVectorElementType() == MVT::i1) {
20924-
Info.FirstVMask = true;
20925-
break;
20926-
}
20927+
constructArgInfos(Ty, FirstVMaskAssigned);
2092720928
}
2092820929

2092920930
void RVVArgDispatcher::allocatePhysReg(unsigned NF, unsigned LMul,

llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1038,33 +1038,33 @@ class RVVArgDispatcher {
10381038
};
10391039

10401040
RVVArgDispatcher(const MachineFunction *MF, const RISCVTargetLowering *TLI,
1041-
std::vector<Type *> &TypeList)
1041+
SmallVectorImpl<Type *> &TypeList)
10421042
: MF(MF), TLI(TLI) {
1043-
construct(TypeList);
1043+
constructArgInfos(TypeList);
10441044
compute();
10451045
}
10461046

10471047
RVVArgDispatcher(const MachineFunction *MF, const RISCVTargetLowering *TLI,
10481048
Type *Ty)
10491049
: MF(MF), TLI(TLI) {
1050-
std::vector<Type *> TypeList = {Ty};
1051-
construct(TypeList);
1050+
SmallVector<Type *, 4> TypeList = {Ty};
1051+
constructArgInfos(TypeList);
10521052
compute();
10531053
}
10541054

10551055
MCPhysReg getNextPhysReg();
10561056

10571057
private:
1058-
std::vector<RVVArgInfo> RVVArgInfos;
1059-
std::vector<MCPhysReg> AllocatedPhysRegs;
1058+
SmallVector<RVVArgInfo, 4> RVVArgInfos;
1059+
SmallVector<MCPhysReg, 4> AllocatedPhysRegs;
10601060

10611061
const MachineFunction *MF = nullptr;
10621062
const RISCVTargetLowering *TLI = nullptr;
10631063

10641064
unsigned CurIdx = 0;
10651065

1066-
void construct(const std::vector<Type *> &TypeList);
1067-
void constructArgInfos(Type *Ty);
1066+
void constructArgInfos(const SmallVectorImpl<Type *> &TypeList);
1067+
void constructArgInfos(Type *Ty, bool &FirstMaskAssigned);
10681068
void compute();
10691069
void allocatePhysReg(unsigned NF = 1, unsigned LMul = 1,
10701070
unsigned StartReg = 0);

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