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[AArch64] Fix failure with inline asm and svcount (#112537)
This fixes an issue where the compiler runs into an assertion failure for the following example: register svcount_t pred asm("pn8") = svptrue_c8(); asm("ld1w { z0.s, z4.s, z8.s, z12.s }, %[pred]/z, [x0]\n" : : [pred] "Uph" (pred) : "memory", "cc"); Here the register constraint that ends up in the LLVM IR is "{pn8}", but the code in `TargetRegisterInfo::getRegForInlineAsmConstraint` that parses that string, follows a path where it queries a suitable register class for this register (<=> PPRorPNR regclass), for which it then chooses `nxv16i1` as a suitable type. These choices individually are correct, but the combined result isn't, because the type should be `aarch64svcount`. This then results in issues later on in SelectionDAGBuilder.cpp in CopyToReg because the type of the actual value and the computed type from the constraint don't match. This PR pre-empts this issue by parsing the predicate explicitly and returning the correct register class.
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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11867,6 +11867,36 @@ const char *AArch64TargetLowering::LowerXConstraint(EVT ConstraintVT) const {
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enum class PredicateConstraint { Uph, Upl, Upa };
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// Returns a {Reg, RegisterClass} tuple if the constraint is
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// a specific predicate register.
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//
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// For some constraint like "{pn3}" the default path in
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// TargetLowering::getRegForInlineAsmConstraint() leads it to determine that a
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// suitable register class for this register is "PPRorPNR", after which it
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// determines that nxv16i1 is an appropriate type for the constraint, which is
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// not what we want. The code here pre-empts this by matching the register
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// explicitly.
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static std::optional<std::pair<unsigned, const TargetRegisterClass *>>
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parsePredicateRegAsConstraint(StringRef Constraint) {
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if (!Constraint.starts_with('{') || !Constraint.ends_with('}') ||
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Constraint[1] != 'p')
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return std::nullopt;
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Constraint = Constraint.substr(2, Constraint.size() - 3);
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bool IsPredicateAsCount = Constraint.starts_with("n");
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if (IsPredicateAsCount)
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Constraint = Constraint.drop_front(1);
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unsigned V;
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if (Constraint.getAsInteger(10, V) || V > 31)
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return std::nullopt;
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if (IsPredicateAsCount)
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return std::make_pair(AArch64::PN0 + V, &AArch64::PNRRegClass);
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else
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return std::make_pair(AArch64::P0 + V, &AArch64::PPRRegClass);
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}
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static std::optional<PredicateConstraint>
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parsePredicateConstraint(StringRef Constraint) {
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return StringSwitch<std::optional<PredicateConstraint>>(Constraint)
@@ -12114,6 +12144,8 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
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break;
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}
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} else {
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if (const auto P = parsePredicateRegAsConstraint(Constraint))
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return *P;
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if (const auto PC = parsePredicateConstraint(Constraint))
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if (const auto *RegClass = getPredicateRegisterClass(*PC, VT))
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return std::make_pair(0U, RegClass);

‎llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,3 +119,67 @@ define <vscale x 8 x half> @test_svfadd_f16_Uph_constraint(<vscale x 16 x i1> %P
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%1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Uph,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
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ret <vscale x 8 x half> %1
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}
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define void @explicit_p0(ptr %p) {
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; CHECK-LABEL: name: explicit_p0
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; CHECK: bb.0 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr = PTRUE_B 31, implicit $vg
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; CHECK-NEXT: $p0 = COPY [[PTRUE_B]]
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
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; CHECK-NEXT: INLINEASM &"ld4w { z0.s, z1.s, z2.s, z3.s }, $1/z, [$0]", 1 /* sideeffect attdialect */, 3538954 /* regdef:GPR64common */, def %1, 9 /* reguse */, $p0, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
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; CHECK-NEXT: RET_ReallyLR
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.b8(i32 31)
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%2 = tail call i64 asm sideeffect "ld4w { z0.s, z1.s, z2.s, z3.s }, $1/z, [$0]", "=r,{p0},0"(<vscale x 16 x i1> %1, ptr %p)
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ret void
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}
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define void @explicit_p8_invalid(ptr %p) {
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; CHECK-LABEL: name: explicit_p8_invalid
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; CHECK: bb.0 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr = PTRUE_B 31, implicit $vg
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; CHECK-NEXT: $p8 = COPY [[PTRUE_B]]
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
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; CHECK-NEXT: INLINEASM &"ld4w { z0.s, z1.s, z2.s, z3.s }, $1/z, [$0]", 1 /* sideeffect attdialect */, 3538954 /* regdef:GPR64common */, def %1, 9 /* reguse */, $p8, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
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; CHECK-NEXT: RET_ReallyLR
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.b8(i32 31)
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%2 = tail call i64 asm sideeffect "ld4w { z0.s, z1.s, z2.s, z3.s }, $1/z, [$0]", "=r,{p8},0"(<vscale x 16 x i1> %1, ptr %p)
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ret void
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}
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define void @explicit_pn8(ptr %p) {
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; CHECK-LABEL: name: explicit_pn8
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; CHECK: bb.0 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: [[PTRUE_C_B:%[0-9]+]]:pnr_p8to15 = PTRUE_C_B implicit $vg
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; CHECK-NEXT: $pn8 = COPY [[PTRUE_C_B]]
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
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; CHECK-NEXT: INLINEASM &"ld1w { z0.s, z4.s, z8.s, z12.s }, $1/z, [$0]", 1 /* sideeffect attdialect */, 3538954 /* regdef:GPR64common */, def %1, 9 /* reguse */, $pn8, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
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; CHECK-NEXT: RET_ReallyLR
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%1 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()
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%2 = tail call i64 asm sideeffect "ld1w { z0.s, z4.s, z8.s, z12.s }, $1/z, [$0]", "=r,{pn8},0"(target("aarch64.svcount") %1, ptr %p)
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ret void
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}
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define void @explicit_pn0_invalid(ptr %p) {
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; CHECK-LABEL: name: explicit_pn0_invalid
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; CHECK: bb.0 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: [[PTRUE_C_B:%[0-9]+]]:pnr_p8to15 = PTRUE_C_B implicit $vg
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; CHECK-NEXT: $pn0 = COPY [[PTRUE_C_B]]
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
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; CHECK-NEXT: INLINEASM &"ld1w { z0.s, z4.s, z8.s, z12.s }, $1/z, [$0]", 1 /* sideeffect attdialect */, 3538954 /* regdef:GPR64common */, def %1, 9 /* reguse */, $pn0, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
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; CHECK-NEXT: RET_ReallyLR
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%1 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()
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%2 = tail call i64 asm sideeffect "ld1w { z0.s, z4.s, z8.s, z12.s }, $1/z, [$0]", "=r,{pn0},0"(target("aarch64.svcount") %1, ptr %p)
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ret void
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}

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