Skip to content

Commit d30a5b4

Browse files
djtodorodjtodoro
authored
[RISCV] Fix xmipscmov extension name (#135647)
The right name was used in riscv-toolchain-conventions docs.
1 parent 0f3e460 commit d30a5b4

File tree

15 files changed

+25
-25
lines changed

15 files changed

+25
-25
lines changed

‎clang/test/Driver/print-supported-extensions-riscv.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@
161161
// CHECK-NEXT: xcvmac 1.0 'XCVmac' (CORE-V Multiply-Accumulate)
162162
// CHECK-NEXT: xcvmem 1.0 'XCVmem' (CORE-V Post-incrementing Load & Store)
163163
// CHECK-NEXT: xcvsimd 1.0 'XCVsimd' (CORE-V SIMD ALU)
164-
// CHECK-NEXT: xmipscmove 1.0 'XMIPSCMove' (MIPS conditional move instruction(s) (ccmov))
164+
// CHECK-NEXT: xmipscmov 1.0 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))
165165
// CHECK-NEXT: xmipslsp 1.0 'XMIPSLSP' (MIPS optimization for hardware load-store bonding)
166166
// CHECK-NEXT: xsfcease 1.0 'XSfcease' (SiFive sf.cease Instruction)
167167
// CHECK-NEXT: xsfvcp 1.0 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)

‎llvm/docs/RISCVUsage.rst

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -491,7 +491,7 @@ The current vendor extensions supported are:
491491
``experimental-Xqcisync``
492492
LLVM implements `version 0.2 of the Qualcomm uC Sync Delay extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
493493

494-
``Xmipscmove``
494+
``Xmipscmov``
495495
LLVM implements conditional move for the `p8700 processor <https://mips.com/products/hardware/p8700/>` by MIPS.
496496

497497
``Xmipslsp``

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -737,8 +737,8 @@ static constexpr DecoderListEntry DecoderList32[]{
737737
{DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"},
738738
{DecoderTableXSfcease32, {RISCV::FeatureVendorXSfcease}, "SiFive sf.cease"},
739739
{DecoderTableXmipslsp32, {RISCV::FeatureVendorXMIPSLSP}, "MIPS mips.lsp"},
740-
{DecoderTableXmipscmove32,
741-
{RISCV::FeatureVendorXMIPSCMove},
740+
{DecoderTableXmipscmov32,
741+
{RISCV::FeatureVendorXMIPSCMov},
742742
"MIPS mips.ccmov"},
743743
// Standard Extensions
744744
{DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1300,12 +1300,12 @@ def HasVendorXCVbi
13001300
"'XCVbi' (CORE-V Immediate Branching)">;
13011301
// MIPS Extensions
13021302

1303-
def FeatureVendorXMIPSCMove
1304-
: RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">;
1305-
def HasVendorXMIPSCMove
1306-
: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
1307-
AssemblerPredicate<(all_of FeatureVendorXMIPSCMove),
1308-
"'Xmipscmove' ('mips.ccmov' instruction)">;
1303+
def FeatureVendorXMIPSCMov
1304+
: RISCVExtension<1, 0, "MIPS conditional move instruction (mips.ccmov)">;
1305+
def HasVendorXMIPSCMov
1306+
: Predicate<"Subtarget->hasVendorXMIPSCMov()">,
1307+
AssemblerPredicate<(all_of FeatureVendorXMIPSCMov),
1308+
"'Xmipscmov' ('mips.ccmov' instruction)">;
13091309
def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
13101310
def FeatureVendorXMIPSLSP
13111311
: RISCVExtension<1, 0, "MIPS optimization for hardware load-store bonding">;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -107,8 +107,8 @@ class SWPFormat<dag outs, dag ins, string opcodestr, string argstr>
107107
// MIPS extensions
108108
//===----------------------------------------------------------------------===//
109109

110-
let Predicates = [HasVendorXMIPSCMove], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
111-
DecoderNamespace = "Xmipscmove" in {
110+
let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
111+
DecoderNamespace = "Xmipscmov" in {
112112
def MIPS_CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
113113
(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
114114
"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,

‎llvm/lib/Target/RISCV/RISCVProcessors.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
119119
FeatureStdExtZbb,
120120
FeatureStdExtZifencei,
121121
FeatureStdExtZicsr,
122-
FeatureVendorXMIPSCMove,
122+
FeatureVendorXMIPSCMov,
123123
FeatureVendorXMIPSLSP],
124124
[TuneMIPSP8700]>;
125125

‎llvm/lib/Target/RISCV/RISCVSubtarget.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -253,5 +253,5 @@ bool RISCVSubtarget::useLoadStorePairs() const {
253253
}
254254

255255
bool RISCVSubtarget::useCCMovInsn() const {
256-
return UseCCMovInsn && HasVendorXMIPSCMove;
256+
return UseCCMovInsn && HasVendorXMIPSCMov;
257257
}

‎llvm/test/CodeGen/RISCV/features-info.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -174,7 +174,7 @@
174174
; CHECK-NEXT: xcvmac - 'XCVmac' (CORE-V Multiply-Accumulate).
175175
; CHECK-NEXT: xcvmem - 'XCVmem' (CORE-V Post-incrementing Load & Store).
176176
; CHECK-NEXT: xcvsimd - 'XCVsimd' (CORE-V SIMD ALU).
177-
; CHECK-NEXT: xmipscmove - 'XMIPSCMove' (MIPS conditional move instruction(s) (ccmov)).
177+
; CHECK-NEXT: xmipscmov - 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov)).
178178
; CHECK-NEXT: xmipslsp - 'XMIPSLSP' (MIPS optimization for hardware load-store bonding).
179179
; CHECK-NEXT: xsfcease - 'XSfcease' (SiFive sf.cease Instruction).
180180
; CHECK-NEXT: xsfvcp - 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions).

‎llvm/test/CodeGen/RISCV/select-and.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
; RUN: | FileCheck -check-prefix=RV32I %s
44
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
55
; RUN: | FileCheck -check-prefix=RV64I %s
6-
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmove -verify-machineinstrs < %s \
6+
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \
77
; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s
88

99
;; There are a few different ways to lower (select (and A, B), X, Y). This test

‎llvm/test/CodeGen/RISCV/select-bare.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
33
; RUN: | FileCheck %s -check-prefix=RV32I
4-
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmove -verify-machineinstrs < %s \
4+
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \
55
; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s
66

77
define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {

‎llvm/test/CodeGen/RISCV/select-cc.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
; RUN: | FileCheck -check-prefixes=RV32I %s
44
; RUN: llc -mtriple=riscv64 -disable-block-placement -verify-machineinstrs < %s \
55
; RUN: | FileCheck -check-prefixes=RV64I %s
6-
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmove -verify-machineinstrs < %s \
6+
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \
77
; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s
88

99
define signext i32 @foo(i32 signext %a, ptr %b) nounwind {

‎llvm/test/CodeGen/RISCV/select-or.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
; RUN: | FileCheck -check-prefix=RV32I %s
44
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
55
; RUN: | FileCheck -check-prefix=RV64I %s
6-
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmove -verify-machineinstrs < %s \
6+
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \
77
; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s
88

99
;; There are a few different ways to lower (select (or A, B), X, Y). This test

‎llvm/test/MC/RISCV/xmips-invalid.s

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# RUN: not llvm-mc -triple=riscv64 < %s 2>&1 | FileCheck %s -check-prefixes=CHECK-FEATURE
2-
# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmove < %s 2>&1 | FileCheck %s
2+
# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov < %s 2>&1 | FileCheck %s
33

44
mips.ccmov x0, x1, 0x10
55
# CHECK: error: invalid operand for instruction
@@ -8,7 +8,7 @@ mips.ccmov x10
88
# CHECK: error: too few operands for instruction
99

1010
mips.ccmov s0, s1, s2, s3
11-
# CHECK-FEATURE: error: instruction requires the following: 'Xmipscmove' ('mips.ccmov' instruction)
11+
# CHECK-FEATURE: error: instruction requires the following: 'Xmipscmov' ('mips.ccmov' instruction)
1212

1313
mips.lwp x10, x11
1414
# CHECK: error: too few operands for instruction

‎llvm/test/MC/RISCV/xmips-valid.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+xmipscmove -M no-aliases -show-encoding \
1+
# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+xmipscmov -M no-aliases -show-encoding \
22
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
3-
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xmipslsp,+xmipscmove < %s \
4-
# RUN: | llvm-objdump --mattr=+xmipslsp,+xmipscmove -M no-aliases -d - \
3+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xmipslsp,+xmipscmov < %s \
4+
# RUN: | llvm-objdump --mattr=+xmipslsp,+xmipscmov -M no-aliases -d - \
55
# RUN: | FileCheck -check-prefix=CHECK-DIS %s
66

77
# CHECK-INST: mips.ccmov s0, s1, s2, s3

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1114,7 +1114,7 @@ R"(All available -march extensions for RISC-V
11141114
xcvmac 1.0
11151115
xcvmem 1.0
11161116
xcvsimd 1.0
1117-
xmipscmove 1.0
1117+
xmipscmov 1.0
11181118
xmipslsp 1.0
11191119
xsfcease 1.0
11201120
xsfvcp 1.0

0 commit comments

Comments
 (0)