@@ -3248,15 +3248,14 @@ InstructionCost AArch64TTIImpl::getVectorInstrCostHelper(
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// Check if the extractelement user is scalar fmul.
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auto IsUserFMulScalarTy = [](const Value *EEUser) {
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// Check if the user is scalar fmul.
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- const auto *BO = dyn_cast_if_present <BinaryOperator>(EEUser);
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+ const auto *BO = dyn_cast <BinaryOperator>(EEUser);
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return BO && BO->getOpcode () == BinaryOperator::FMul &&
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!BO->getType ()->isVectorTy ();
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};
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// Check if the extract index is from lane 0 or lane equivalent to 0 for a
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// certain scalar type and a certain vector register width.
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- auto IsExtractLaneEquivalentToZero = [&](const unsigned &Idx,
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- const unsigned &EltSz) {
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+ auto IsExtractLaneEquivalentToZero = [&](unsigned Idx, unsigned EltSz) {
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auto RegWidth =
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getRegisterBitWidth (TargetTransformInfo::RGK_FixedWidthVector)
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.getFixedValue ();
@@ -3277,13 +3276,15 @@ InstructionCost AArch64TTIImpl::getVectorInstrCostHelper(
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// important.
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UserToExtractIdx[U];
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}
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+ if (UserToExtractIdx.empty ())
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+ return false ;
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for (auto &[S, U, L] : ScalarUserAndIdx) {
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for (auto *U : S->users ()) {
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if (UserToExtractIdx.find (U) != UserToExtractIdx.end ()) {
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auto *FMul = cast<BinaryOperator>(U);
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auto *Op0 = FMul->getOperand (0 );
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auto *Op1 = FMul->getOperand (1 );
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- if ((Op0 == S && Op1 == S) || ( Op0 != S) || ( Op1 != S) ) {
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+ if ((Op0 == S && Op1 == S) || Op0 != S || Op1 != S) {
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UserToExtractIdx[U] = L;
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break ;
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}
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