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[GlobalISel][Mips] Global ISel for brcond
- Enable equivalent between `brcond` and `G_BRCOND`. - Remove the manual selection of `G_BRCOND` in Mips. Revise test cases. Reviewers: petar-avramovic, bcardosolopes, arsenm Reviewed By: arsenm Pull Request: #81306
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5 files changed

+176
-147
lines changed

5 files changed

+176
-147
lines changed

‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

+1
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,7 @@ let IfConvergent = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS in {
130130
}
131131

132132
def : GINodeEquiv<G_BR, br>;
133+
def : GINodeEquiv<G_BRCOND, brcond>;
133134
def : GINodeEquiv<G_BSWAP, bswap>;
134135
def : GINodeEquiv<G_BITREVERSE, bitreverse>;
135136
def : GINodeEquiv<G_FSHL, fshl>;

‎llvm/lib/Target/Mips/MipsInstructionSelector.cpp

-7
Original file line numberDiff line numberDiff line change
@@ -357,13 +357,6 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
357357
.addImm(0);
358358
break;
359359
}
360-
case G_BRCOND: {
361-
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE))
362-
.add(I.getOperand(0))
363-
.addUse(Mips::ZERO)
364-
.add(I.getOperand(1));
365-
break;
366-
}
367360
case G_BRJT: {
368361
unsigned EntrySize =
369362
MF.getJumpTableInfo()->getEntrySize(MF.getDataLayout());

‎llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir

+1-1
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ body: |
7777
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
7878
; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
7979
; MIPS32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
80-
; MIPS32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
80+
; MIPS32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
8181
; MIPS32-NEXT: J %bb.2, implicit-def dead $at
8282
; MIPS32-NEXT: {{ $}}
8383
; MIPS32-NEXT: bb.1.if.then:

‎llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir

+166-131
Original file line numberDiff line numberDiff line change
@@ -73,139 +73,174 @@ jumpTable:
7373
body: |
7474
; MIPS32-LABEL: name: mod4_0_to_11
7575
; MIPS32: bb.0.entry:
76-
; MIPS32: successors: %bb.6(0x40000000), %bb.1(0x40000000)
77-
; MIPS32: liveins: $a0
78-
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
79-
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
80-
; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
81-
; MIPS32: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
82-
; MIPS32: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
83-
; MIPS32: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
84-
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
85-
; MIPS32: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
86-
; MIPS32: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
87-
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
88-
; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
89-
; MIPS32: BNE [[ANDi]], $zero, %bb.6, implicit-def $at
90-
; MIPS32: bb.1.entry:
91-
; MIPS32: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
92-
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.0
93-
; MIPS32: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
94-
; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[LUi]], [[SLL]]
95-
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32))
96-
; MIPS32: PseudoIndirectBranch [[LW]]
97-
; MIPS32: bb.2.sw.bb:
98-
; MIPS32: $v0 = COPY [[ORi4]]
99-
; MIPS32: RetRA implicit $v0
100-
; MIPS32: bb.3.sw.bb1:
101-
; MIPS32: $v0 = COPY [[ORi3]]
102-
; MIPS32: RetRA implicit $v0
103-
; MIPS32: bb.4.sw.bb2:
104-
; MIPS32: $v0 = COPY [[ORi2]]
105-
; MIPS32: RetRA implicit $v0
106-
; MIPS32: bb.5.sw.bb3:
107-
; MIPS32: $v0 = COPY [[ORi1]]
108-
; MIPS32: RetRA implicit $v0
109-
; MIPS32: bb.6.sw.default:
110-
; MIPS32: successors: %bb.7(0x80000000)
111-
; MIPS32: bb.7.sw.epilog:
112-
; MIPS32: successors: %bb.13(0x40000000), %bb.8(0x40000000)
113-
; MIPS32: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
114-
; MIPS32: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
115-
; MIPS32: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
116-
; MIPS32: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
117-
; MIPS32: BNE [[ANDi1]], $zero, %bb.13, implicit-def $at
118-
; MIPS32: bb.8.sw.epilog:
119-
; MIPS32: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
120-
; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.1
121-
; MIPS32: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
122-
; MIPS32: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LUi1]], [[SLL1]]
123-
; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32))
124-
; MIPS32: PseudoIndirectBranch [[LW1]]
125-
; MIPS32: bb.9.sw.bb4:
126-
; MIPS32: $v0 = COPY [[ORi4]]
127-
; MIPS32: RetRA implicit $v0
128-
; MIPS32: bb.10.sw.bb5:
129-
; MIPS32: $v0 = COPY [[ORi3]]
130-
; MIPS32: RetRA implicit $v0
131-
; MIPS32: bb.11.sw.bb6:
132-
; MIPS32: $v0 = COPY [[ORi2]]
133-
; MIPS32: RetRA implicit $v0
134-
; MIPS32: bb.12.sw.bb7:
135-
; MIPS32: $v0 = COPY [[ORi1]]
136-
; MIPS32: RetRA implicit $v0
137-
; MIPS32: bb.13.sw.default8:
138-
; MIPS32: $v0 = COPY [[ADDiu]]
139-
; MIPS32: RetRA implicit $v0
76+
; MIPS32-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000)
77+
; MIPS32-NEXT: liveins: $a0
78+
; MIPS32-NEXT: {{ $}}
79+
; MIPS32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
80+
; MIPS32-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
81+
; MIPS32-NEXT: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
82+
; MIPS32-NEXT: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
83+
; MIPS32-NEXT: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
84+
; MIPS32-NEXT: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
85+
; MIPS32-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
86+
; MIPS32-NEXT: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
87+
; MIPS32-NEXT: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
88+
; MIPS32-NEXT: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
89+
; MIPS32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
90+
; MIPS32-NEXT: BNE [[ANDi]], $zero, %bb.6, implicit-def dead $at
91+
; MIPS32-NEXT: {{ $}}
92+
; MIPS32-NEXT: bb.1.entry:
93+
; MIPS32-NEXT: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
94+
; MIPS32-NEXT: {{ $}}
95+
; MIPS32-NEXT: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.0
96+
; MIPS32-NEXT: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
97+
; MIPS32-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[LUi]], [[SLL]]
98+
; MIPS32-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32))
99+
; MIPS32-NEXT: PseudoIndirectBranch [[LW]]
100+
; MIPS32-NEXT: {{ $}}
101+
; MIPS32-NEXT: bb.2.sw.bb:
102+
; MIPS32-NEXT: $v0 = COPY [[ORi4]]
103+
; MIPS32-NEXT: RetRA implicit $v0
104+
; MIPS32-NEXT: {{ $}}
105+
; MIPS32-NEXT: bb.3.sw.bb1:
106+
; MIPS32-NEXT: $v0 = COPY [[ORi3]]
107+
; MIPS32-NEXT: RetRA implicit $v0
108+
; MIPS32-NEXT: {{ $}}
109+
; MIPS32-NEXT: bb.4.sw.bb2:
110+
; MIPS32-NEXT: $v0 = COPY [[ORi2]]
111+
; MIPS32-NEXT: RetRA implicit $v0
112+
; MIPS32-NEXT: {{ $}}
113+
; MIPS32-NEXT: bb.5.sw.bb3:
114+
; MIPS32-NEXT: $v0 = COPY [[ORi1]]
115+
; MIPS32-NEXT: RetRA implicit $v0
116+
; MIPS32-NEXT: {{ $}}
117+
; MIPS32-NEXT: bb.6.sw.default:
118+
; MIPS32-NEXT: successors: %bb.7(0x80000000)
119+
; MIPS32-NEXT: {{ $}}
120+
; MIPS32-NEXT: bb.7.sw.epilog:
121+
; MIPS32-NEXT: successors: %bb.13(0x40000000), %bb.8(0x40000000)
122+
; MIPS32-NEXT: {{ $}}
123+
; MIPS32-NEXT: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
124+
; MIPS32-NEXT: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
125+
; MIPS32-NEXT: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
126+
; MIPS32-NEXT: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
127+
; MIPS32-NEXT: BNE [[ANDi1]], $zero, %bb.13, implicit-def dead $at
128+
; MIPS32-NEXT: {{ $}}
129+
; MIPS32-NEXT: bb.8.sw.epilog:
130+
; MIPS32-NEXT: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
131+
; MIPS32-NEXT: {{ $}}
132+
; MIPS32-NEXT: [[LUi1:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.1
133+
; MIPS32-NEXT: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
134+
; MIPS32-NEXT: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LUi1]], [[SLL1]]
135+
; MIPS32-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32))
136+
; MIPS32-NEXT: PseudoIndirectBranch [[LW1]]
137+
; MIPS32-NEXT: {{ $}}
138+
; MIPS32-NEXT: bb.9.sw.bb4:
139+
; MIPS32-NEXT: $v0 = COPY [[ORi4]]
140+
; MIPS32-NEXT: RetRA implicit $v0
141+
; MIPS32-NEXT: {{ $}}
142+
; MIPS32-NEXT: bb.10.sw.bb5:
143+
; MIPS32-NEXT: $v0 = COPY [[ORi3]]
144+
; MIPS32-NEXT: RetRA implicit $v0
145+
; MIPS32-NEXT: {{ $}}
146+
; MIPS32-NEXT: bb.11.sw.bb6:
147+
; MIPS32-NEXT: $v0 = COPY [[ORi2]]
148+
; MIPS32-NEXT: RetRA implicit $v0
149+
; MIPS32-NEXT: {{ $}}
150+
; MIPS32-NEXT: bb.12.sw.bb7:
151+
; MIPS32-NEXT: $v0 = COPY [[ORi1]]
152+
; MIPS32-NEXT: RetRA implicit $v0
153+
; MIPS32-NEXT: {{ $}}
154+
; MIPS32-NEXT: bb.13.sw.default8:
155+
; MIPS32-NEXT: $v0 = COPY [[ADDiu]]
156+
; MIPS32-NEXT: RetRA implicit $v0
157+
;
140158
; MIPS32_PIC-LABEL: name: mod4_0_to_11
141159
; MIPS32_PIC: bb.0.entry:
142-
; MIPS32_PIC: successors: %bb.6(0x40000000), %bb.1(0x40000000)
143-
; MIPS32_PIC: liveins: $a0, $t9, $v0
144-
; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
145-
; MIPS32_PIC: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
146-
; MIPS32_PIC: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
147-
; MIPS32_PIC: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
148-
; MIPS32_PIC: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
149-
; MIPS32_PIC: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
150-
; MIPS32_PIC: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
151-
; MIPS32_PIC: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
152-
; MIPS32_PIC: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
153-
; MIPS32_PIC: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
154-
; MIPS32_PIC: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
155-
; MIPS32_PIC: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
156-
; MIPS32_PIC: BNE [[ANDi]], $zero, %bb.6, implicit-def $at
157-
; MIPS32_PIC: bb.1.entry:
158-
; MIPS32_PIC: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
159-
; MIPS32_PIC: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.0 :: (load (s32) from got)
160-
; MIPS32_PIC: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
161-
; MIPS32_PIC: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LW]], [[SLL]]
162-
; MIPS32_PIC: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32))
163-
; MIPS32_PIC: [[ADDu2:%[0-9]+]]:gpr32 = ADDu [[LW1]], [[ADDu]]
164-
; MIPS32_PIC: PseudoIndirectBranch [[ADDu2]]
165-
; MIPS32_PIC: bb.2.sw.bb:
166-
; MIPS32_PIC: $v0 = COPY [[ORi4]]
167-
; MIPS32_PIC: RetRA implicit $v0
168-
; MIPS32_PIC: bb.3.sw.bb1:
169-
; MIPS32_PIC: $v0 = COPY [[ORi3]]
170-
; MIPS32_PIC: RetRA implicit $v0
171-
; MIPS32_PIC: bb.4.sw.bb2:
172-
; MIPS32_PIC: $v0 = COPY [[ORi2]]
173-
; MIPS32_PIC: RetRA implicit $v0
174-
; MIPS32_PIC: bb.5.sw.bb3:
175-
; MIPS32_PIC: $v0 = COPY [[ORi1]]
176-
; MIPS32_PIC: RetRA implicit $v0
177-
; MIPS32_PIC: bb.6.sw.default:
178-
; MIPS32_PIC: successors: %bb.7(0x80000000)
179-
; MIPS32_PIC: bb.7.sw.epilog:
180-
; MIPS32_PIC: successors: %bb.13(0x40000000), %bb.8(0x40000000)
181-
; MIPS32_PIC: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
182-
; MIPS32_PIC: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
183-
; MIPS32_PIC: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
184-
; MIPS32_PIC: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
185-
; MIPS32_PIC: BNE [[ANDi1]], $zero, %bb.13, implicit-def $at
186-
; MIPS32_PIC: bb.8.sw.epilog:
187-
; MIPS32_PIC: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
188-
; MIPS32_PIC: [[LW2:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.1 :: (load (s32) from got)
189-
; MIPS32_PIC: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
190-
; MIPS32_PIC: [[ADDu3:%[0-9]+]]:gpr32 = ADDu [[LW2]], [[SLL1]]
191-
; MIPS32_PIC: [[LW3:%[0-9]+]]:gpr32 = LW [[ADDu3]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32))
192-
; MIPS32_PIC: [[ADDu4:%[0-9]+]]:gpr32 = ADDu [[LW3]], [[ADDu]]
193-
; MIPS32_PIC: PseudoIndirectBranch [[ADDu4]]
194-
; MIPS32_PIC: bb.9.sw.bb4:
195-
; MIPS32_PIC: $v0 = COPY [[ORi4]]
196-
; MIPS32_PIC: RetRA implicit $v0
197-
; MIPS32_PIC: bb.10.sw.bb5:
198-
; MIPS32_PIC: $v0 = COPY [[ORi3]]
199-
; MIPS32_PIC: RetRA implicit $v0
200-
; MIPS32_PIC: bb.11.sw.bb6:
201-
; MIPS32_PIC: $v0 = COPY [[ORi2]]
202-
; MIPS32_PIC: RetRA implicit $v0
203-
; MIPS32_PIC: bb.12.sw.bb7:
204-
; MIPS32_PIC: $v0 = COPY [[ORi1]]
205-
; MIPS32_PIC: RetRA implicit $v0
206-
; MIPS32_PIC: bb.13.sw.default8:
207-
; MIPS32_PIC: $v0 = COPY [[ADDiu]]
208-
; MIPS32_PIC: RetRA implicit $v0
160+
; MIPS32_PIC-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000)
161+
; MIPS32_PIC-NEXT: liveins: $a0, $t9, $v0
162+
; MIPS32_PIC-NEXT: {{ $}}
163+
; MIPS32_PIC-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
164+
; MIPS32_PIC-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
165+
; MIPS32_PIC-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
166+
; MIPS32_PIC-NEXT: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
167+
; MIPS32_PIC-NEXT: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
168+
; MIPS32_PIC-NEXT: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
169+
; MIPS32_PIC-NEXT: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
170+
; MIPS32_PIC-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
171+
; MIPS32_PIC-NEXT: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
172+
; MIPS32_PIC-NEXT: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
173+
; MIPS32_PIC-NEXT: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
174+
; MIPS32_PIC-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
175+
; MIPS32_PIC-NEXT: BNE [[ANDi]], $zero, %bb.6, implicit-def dead $at
176+
; MIPS32_PIC-NEXT: {{ $}}
177+
; MIPS32_PIC-NEXT: bb.1.entry:
178+
; MIPS32_PIC-NEXT: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
179+
; MIPS32_PIC-NEXT: {{ $}}
180+
; MIPS32_PIC-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.0 :: (load (s32) from got)
181+
; MIPS32_PIC-NEXT: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
182+
; MIPS32_PIC-NEXT: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LW]], [[SLL]]
183+
; MIPS32_PIC-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32))
184+
; MIPS32_PIC-NEXT: [[ADDu2:%[0-9]+]]:gpr32 = ADDu [[LW1]], [[ADDu]]
185+
; MIPS32_PIC-NEXT: PseudoIndirectBranch [[ADDu2]]
186+
; MIPS32_PIC-NEXT: {{ $}}
187+
; MIPS32_PIC-NEXT: bb.2.sw.bb:
188+
; MIPS32_PIC-NEXT: $v0 = COPY [[ORi4]]
189+
; MIPS32_PIC-NEXT: RetRA implicit $v0
190+
; MIPS32_PIC-NEXT: {{ $}}
191+
; MIPS32_PIC-NEXT: bb.3.sw.bb1:
192+
; MIPS32_PIC-NEXT: $v0 = COPY [[ORi3]]
193+
; MIPS32_PIC-NEXT: RetRA implicit $v0
194+
; MIPS32_PIC-NEXT: {{ $}}
195+
; MIPS32_PIC-NEXT: bb.4.sw.bb2:
196+
; MIPS32_PIC-NEXT: $v0 = COPY [[ORi2]]
197+
; MIPS32_PIC-NEXT: RetRA implicit $v0
198+
; MIPS32_PIC-NEXT: {{ $}}
199+
; MIPS32_PIC-NEXT: bb.5.sw.bb3:
200+
; MIPS32_PIC-NEXT: $v0 = COPY [[ORi1]]
201+
; MIPS32_PIC-NEXT: RetRA implicit $v0
202+
; MIPS32_PIC-NEXT: {{ $}}
203+
; MIPS32_PIC-NEXT: bb.6.sw.default:
204+
; MIPS32_PIC-NEXT: successors: %bb.7(0x80000000)
205+
; MIPS32_PIC-NEXT: {{ $}}
206+
; MIPS32_PIC-NEXT: bb.7.sw.epilog:
207+
; MIPS32_PIC-NEXT: successors: %bb.13(0x40000000), %bb.8(0x40000000)
208+
; MIPS32_PIC-NEXT: {{ $}}
209+
; MIPS32_PIC-NEXT: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
210+
; MIPS32_PIC-NEXT: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
211+
; MIPS32_PIC-NEXT: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
212+
; MIPS32_PIC-NEXT: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
213+
; MIPS32_PIC-NEXT: BNE [[ANDi1]], $zero, %bb.13, implicit-def dead $at
214+
; MIPS32_PIC-NEXT: {{ $}}
215+
; MIPS32_PIC-NEXT: bb.8.sw.epilog:
216+
; MIPS32_PIC-NEXT: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
217+
; MIPS32_PIC-NEXT: {{ $}}
218+
; MIPS32_PIC-NEXT: [[LW2:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.1 :: (load (s32) from got)
219+
; MIPS32_PIC-NEXT: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
220+
; MIPS32_PIC-NEXT: [[ADDu3:%[0-9]+]]:gpr32 = ADDu [[LW2]], [[SLL1]]
221+
; MIPS32_PIC-NEXT: [[LW3:%[0-9]+]]:gpr32 = LW [[ADDu3]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32))
222+
; MIPS32_PIC-NEXT: [[ADDu4:%[0-9]+]]:gpr32 = ADDu [[LW3]], [[ADDu]]
223+
; MIPS32_PIC-NEXT: PseudoIndirectBranch [[ADDu4]]
224+
; MIPS32_PIC-NEXT: {{ $}}
225+
; MIPS32_PIC-NEXT: bb.9.sw.bb4:
226+
; MIPS32_PIC-NEXT: $v0 = COPY [[ORi4]]
227+
; MIPS32_PIC-NEXT: RetRA implicit $v0
228+
; MIPS32_PIC-NEXT: {{ $}}
229+
; MIPS32_PIC-NEXT: bb.10.sw.bb5:
230+
; MIPS32_PIC-NEXT: $v0 = COPY [[ORi3]]
231+
; MIPS32_PIC-NEXT: RetRA implicit $v0
232+
; MIPS32_PIC-NEXT: {{ $}}
233+
; MIPS32_PIC-NEXT: bb.11.sw.bb6:
234+
; MIPS32_PIC-NEXT: $v0 = COPY [[ORi2]]
235+
; MIPS32_PIC-NEXT: RetRA implicit $v0
236+
; MIPS32_PIC-NEXT: {{ $}}
237+
; MIPS32_PIC-NEXT: bb.12.sw.bb7:
238+
; MIPS32_PIC-NEXT: $v0 = COPY [[ORi1]]
239+
; MIPS32_PIC-NEXT: RetRA implicit $v0
240+
; MIPS32_PIC-NEXT: {{ $}}
241+
; MIPS32_PIC-NEXT: bb.13.sw.default8:
242+
; MIPS32_PIC-NEXT: $v0 = COPY [[ADDiu]]
243+
; MIPS32_PIC-NEXT: RetRA implicit $v0
209244
bb.1.entry:
210245
liveins: $a0
211246

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