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[RISCV] Update implies for subtarget feature. (#75824)
PR #75576 and #75735 update some implies in llvm/lib/Support/RISCVISAInfo.cpp, but both of them miss the subtarget feature part. This patch still preserve predicate HasStdExtZfhOrZfhmin and HasStdExtZhinxOrZhinxmin, since they could make error message more readable. ( Users might not know that zfh implies zfhmin.)
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+33
-40
lines changed

5 files changed

+33
-40
lines changed

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -107,15 +107,15 @@ def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
107107
def FeatureStdExtZfh
108108
: SubtargetFeature<"zfh", "HasStdExtZfh", "true",
109109
"'Zfh' (Half-Precision Floating-Point)",
110-
[FeatureStdExtF]>;
110+
[FeatureStdExtZfhmin]>;
111111
def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
112112
AssemblerPredicate<(all_of FeatureStdExtZfh),
113113
"'Zfh' (Half-Precision Floating-Point)">;
114114
def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
115115

116116
def HasStdExtZfhOrZfhmin
117-
: Predicate<"Subtarget->hasStdExtZfhOrZfhmin()">,
118-
AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin),
117+
: Predicate<"Subtarget->hasStdExtZfhmin()">,
118+
AssemblerPredicate<(all_of FeatureStdExtZfhmin),
119119
"'Zfh' (Half-Precision Floating-Point) or "
120120
"'Zfhmin' (Half-Precision Floating-Point Minimal)">;
121121

@@ -146,15 +146,15 @@ def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
146146
def FeatureStdExtZhinx
147147
: SubtargetFeature<"zhinx", "HasStdExtZhinx", "true",
148148
"'Zhinx' (Half Float in Integer)",
149-
[FeatureStdExtZfinx]>;
149+
[FeatureStdExtZhinxmin]>;
150150
def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
151151
AssemblerPredicate<(all_of FeatureStdExtZhinx),
152152
"'Zhinx' (Half Float in Integer)">;
153153
def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
154154

155155
def HasStdExtZhinxOrZhinxmin
156-
: Predicate<"Subtarget->hasStdExtZhinx() || Subtarget->hasStdExtZhinxmin()">,
157-
AssemblerPredicate<(any_of FeatureStdExtZhinx, FeatureStdExtZhinxmin),
156+
: Predicate<"Subtarget->hasStdExtZhinxmin()">,
157+
AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
158158
"'Zhinx' (Half Float in Integer) or "
159159
"'Zhinxmin' (Half Float in Integer Minimal)">;
160160

@@ -487,16 +487,16 @@ def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
487487

488488
def HasVInstructionsBF16 : Predicate<"Subtarget->hasVInstructionsBF16()">;
489489

490-
def FeatureStdExtZvfh
491-
: SubtargetFeature<"zvfh", "HasStdExtZvfh", "true",
492-
"'Zvfh' (Vector Half-Precision Floating-Point)",
493-
[FeatureStdExtZve32f, FeatureStdExtZfhmin]>;
494-
495490
def FeatureStdExtZvfhmin
496491
: SubtargetFeature<"zvfhmin", "HasStdExtZvfhmin", "true",
497492
"'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
498493
[FeatureStdExtZve32f]>;
499494

495+
def FeatureStdExtZvfh
496+
: SubtargetFeature<"zvfh", "HasStdExtZvfh", "true",
497+
"'Zvfh' (Vector Half-Precision Floating-Point)",
498+
[FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>;
499+
500500
def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
501501

502502
def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minimal()">,

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -915,8 +915,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
915915
Opc = RISCV::FMV_H_X;
916916
break;
917917
case MVT::f16:
918-
Opc =
919-
Subtarget->hasStdExtZhinxOrZhinxmin() ? RISCV::COPY : RISCV::FMV_H_X;
918+
Opc = Subtarget->hasStdExtZhinxmin() ? RISCV::COPY : RISCV::FMV_H_X;
920919
break;
921920
case MVT::f32:
922921
Opc = Subtarget->hasStdExtZfinx() ? RISCV::COPY : RISCV::FMV_W_X;

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -122,15 +122,15 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
122122
if (Subtarget.is64Bit() && RV64LegalI32)
123123
addRegisterClass(MVT::i32, &RISCV::GPRRegClass);
124124

125-
if (Subtarget.hasStdExtZfhOrZfhmin())
125+
if (Subtarget.hasStdExtZfhmin())
126126
addRegisterClass(MVT::f16, &RISCV::FPR16RegClass);
127127
if (Subtarget.hasStdExtZfbfmin())
128128
addRegisterClass(MVT::bf16, &RISCV::FPR16RegClass);
129129
if (Subtarget.hasStdExtF())
130130
addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
131131
if (Subtarget.hasStdExtD())
132132
addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
133-
if (Subtarget.hasStdExtZhinxOrZhinxmin())
133+
if (Subtarget.hasStdExtZhinxmin())
134134
addRegisterClass(MVT::f16, &RISCV::GPRF16RegClass);
135135
if (Subtarget.hasStdExtZfinx())
136136
addRegisterClass(MVT::f32, &RISCV::GPRF32RegClass);
@@ -439,7 +439,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
439439
ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FRINT, ISD::FROUND,
440440
ISD::FROUNDEVEN};
441441

442-
if (Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin())
442+
if (Subtarget.hasStdExtZfhminOrZhinxmin())
443443
setOperationAction(ISD::BITCAST, MVT::i16, Custom);
444444

445445
static const unsigned ZfhminZfbfminPromoteOps[] = {
@@ -469,7 +469,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
469469
setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Expand);
470470
}
471471

472-
if (Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin()) {
472+
if (Subtarget.hasStdExtZfhminOrZhinxmin()) {
473473
if (Subtarget.hasStdExtZfhOrZhinx()) {
474474
setOperationAction(FPLegalNodeTypes, MVT::f16, Legal);
475475
setOperationAction(FPRndMode, MVT::f16,
@@ -1322,7 +1322,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
13221322
// Custom-legalize bitcasts from fixed-length vectors to scalar types.
13231323
setOperationAction(ISD::BITCAST, {MVT::i8, MVT::i16, MVT::i32, MVT::i64},
13241324
Custom);
1325-
if (Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin())
1325+
if (Subtarget.hasStdExtZfhminOrZhinxmin())
13261326
setOperationAction(ISD::BITCAST, MVT::f16, Custom);
13271327
if (Subtarget.hasStdExtFOrZfinx())
13281328
setOperationAction(ISD::BITCAST, MVT::f32, Custom);
@@ -1388,7 +1388,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
13881388

13891389
if (Subtarget.hasStdExtZbkb())
13901390
setTargetDAGCombine(ISD::BITREVERSE);
1391-
if (Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin())
1391+
if (Subtarget.hasStdExtZfhminOrZhinxmin())
13921392
setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
13931393
if (Subtarget.hasStdExtFOrZfinx())
13941394
setTargetDAGCombine({ISD::ZERO_EXTEND, ISD::FP_TO_SINT, ISD::FP_TO_UINT,
@@ -2099,7 +2099,7 @@ bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
20992099
bool ForCodeSize) const {
21002100
bool IsLegalVT = false;
21012101
if (VT == MVT::f16)
2102-
IsLegalVT = Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin();
2102+
IsLegalVT = Subtarget.hasStdExtZfhminOrZhinxmin();
21032103
else if (VT == MVT::f32)
21042104
IsLegalVT = Subtarget.hasStdExtFOrZfinx();
21052105
else if (VT == MVT::f64)
@@ -2171,7 +2171,7 @@ MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
21712171
// Use f32 to pass f16 if it is legal and Zfh/Zfhmin is not enabled.
21722172
// We might still end up using a GPR but that will be decided based on ABI.
21732173
if (VT == MVT::f16 && Subtarget.hasStdExtFOrZfinx() &&
2174-
!Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin())
2174+
!Subtarget.hasStdExtZfhminOrZhinxmin())
21752175
return MVT::f32;
21762176

21772177
MVT PartVT = TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
@@ -2188,7 +2188,7 @@ unsigned RISCVTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context
21882188
// Use f32 to pass f16 if it is legal and Zfh/Zfhmin is not enabled.
21892189
// We might still end up using a GPR but that will be decided based on ABI.
21902190
if (VT == MVT::f16 && Subtarget.hasStdExtFOrZfinx() &&
2191-
!Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin())
2191+
!Subtarget.hasStdExtZfhminOrZhinxmin())
21922192
return 1;
21932193

21942194
return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
@@ -5761,7 +5761,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
57615761
EVT Op0VT = Op0.getValueType();
57625762
MVT XLenVT = Subtarget.getXLenVT();
57635763
if (VT == MVT::f16 && Op0VT == MVT::i16 &&
5764-
Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin()) {
5764+
Subtarget.hasStdExtZfhminOrZhinxmin()) {
57655765
SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Op0);
57665766
SDValue FPConv = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, NewOp0);
57675767
return FPConv;
@@ -11527,11 +11527,11 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
1152711527
EVT Op0VT = Op0.getValueType();
1152811528
MVT XLenVT = Subtarget.getXLenVT();
1152911529
if (VT == MVT::i16 && Op0VT == MVT::f16 &&
11530-
Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin()) {
11530+
Subtarget.hasStdExtZfhminOrZhinxmin()) {
1153111531
SDValue FPConv = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenVT, Op0);
1153211532
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FPConv));
1153311533
} else if (VT == MVT::i16 && Op0VT == MVT::bf16 &&
11534-
Subtarget.hasStdExtZfbfmin()) {
11534+
Subtarget.hasStdExtZfbfmin()) {
1153511535
SDValue FPConv = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenVT, Op0);
1153611536
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FPConv));
1153711537
} else if (VT == MVT::i32 && Op0VT == MVT::f32 && Subtarget.is64Bit() &&
@@ -18632,15 +18632,15 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1863218632
// TODO: Support fixed vectors up to XLen for P extension?
1863318633
if (VT.isVector())
1863418634
break;
18635-
if (VT == MVT::f16 && Subtarget.hasStdExtZhinxOrZhinxmin())
18635+
if (VT == MVT::f16 && Subtarget.hasStdExtZhinxmin())
1863618636
return std::make_pair(0U, &RISCV::GPRF16RegClass);
1863718637
if (VT == MVT::f32 && Subtarget.hasStdExtZfinx())
1863818638
return std::make_pair(0U, &RISCV::GPRF32RegClass);
1863918639
if (VT == MVT::f64 && Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit())
1864018640
return std::make_pair(0U, &RISCV::GPRPF64RegClass);
1864118641
return std::make_pair(0U, &RISCV::GPRNoX0RegClass);
1864218642
case 'f':
18643-
if (Subtarget.hasStdExtZfhOrZfhmin() && VT == MVT::f16)
18643+
if (Subtarget.hasStdExtZfhmin() && VT == MVT::f16)
1864418644
return std::make_pair(0U, &RISCV::FPR16RegClass);
1864518645
if (Subtarget.hasStdExtF() && VT == MVT::f32)
1864618646
return std::make_pair(0U, &RISCV::FPR32RegClass);
@@ -18753,7 +18753,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1875318753
}
1875418754
if (VT == MVT::f32 || VT == MVT::Other)
1875518755
return std::make_pair(FReg, &RISCV::FPR32RegClass);
18756-
if (Subtarget.hasStdExtZfhOrZfhmin() && VT == MVT::f16) {
18756+
if (Subtarget.hasStdExtZfhmin() && VT == MVT::f16) {
1875718757
unsigned RegNo = FReg - RISCV::F0_F;
1875818758
unsigned HReg = RISCV::F0_H + RegNo;
1875918759
return std::make_pair(HReg, &RISCV::FPR16RegClass);
@@ -19100,7 +19100,7 @@ bool RISCVTargetLowering::shouldConvertFpToSat(unsigned Op, EVT FPVT,
1910019100

1910119101
switch (FPVT.getSimpleVT().SimpleTy) {
1910219102
case MVT::f16:
19103-
return Subtarget.hasStdExtZfhOrZfhmin();
19103+
return Subtarget.hasStdExtZfhmin();
1910419104
case MVT::f32:
1910519105
return Subtarget.hasStdExtF();
1910619106
case MVT::f64:

‎llvm/lib/Target/RISCV/RISCVSubtarget.h

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -143,16 +143,12 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
143143
bool hasStdExtZvl() const { return ZvlLen != 0; }
144144
bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
145145
bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }
146-
bool hasStdExtZfhOrZfhmin() const { return HasStdExtZfh || HasStdExtZfhmin; }
147146
bool hasStdExtZfhOrZhinx() const { return HasStdExtZfh || HasStdExtZhinx; }
148-
bool hasStdExtZhinxOrZhinxmin() const {
149-
return HasStdExtZhinx || HasStdExtZhinxmin;
150-
}
151-
bool hasStdExtZfhOrZfhminOrZhinxOrZhinxmin() const {
152-
return hasStdExtZfhOrZfhmin() || hasStdExtZhinxOrZhinxmin();
147+
bool hasStdExtZfhminOrZhinxmin() const {
148+
return HasStdExtZfhmin || HasStdExtZhinxmin;
153149
}
154150
bool hasHalfFPLoadStoreMove() const {
155-
return hasStdExtZfhOrZfhmin() || HasStdExtZfbfmin;
151+
return HasStdExtZfhmin || HasStdExtZfbfmin;
156152
}
157153
bool is64Bit() const { return IsRV64; }
158154
MVT getXLenVT() const {
@@ -201,9 +197,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
201197
// Vector codegen related methods.
202198
bool hasVInstructions() const { return HasStdExtZve32x; }
203199
bool hasVInstructionsI64() const { return HasStdExtZve64x; }
204-
bool hasVInstructionsF16Minimal() const {
205-
return HasStdExtZvfhmin || HasStdExtZvfh;
206-
}
200+
bool hasVInstructionsF16Minimal() const { return HasStdExtZvfhmin; }
207201
bool hasVInstructionsF16() const { return HasStdExtZvfh; }
208202
bool hasVInstructionsBF16() const { return HasStdExtZvfbfmin; }
209203
bool hasVInstructionsF32() const { return HasStdExtZve32f; }

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -334,7 +334,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
334334
return RISCVRegisterClass::GPRRC;
335335

336336
Type *ScalarTy = Ty->getScalarType();
337-
if ((ScalarTy->isHalfTy() && ST->hasStdExtZfhOrZfhmin()) ||
337+
if ((ScalarTy->isHalfTy() && ST->hasStdExtZfhmin()) ||
338338
(ScalarTy->isFloatTy() && ST->hasStdExtF()) ||
339339
(ScalarTy->isDoubleTy() && ST->hasStdExtD())) {
340340
return RISCVRegisterClass::FPRRC;

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