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andjo403andjo403
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[AMDGPU] Swap range metadata to attribute for workitem id. (#94871)
Swap out range metadata to range attribute for calls to be able to deprecate range metadata on calls in the future.
1 parent 5bb9c08 commit cc19374

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5 files changed

+72
-74
lines changed

5 files changed

+72
-74
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -560,10 +560,16 @@ bool AMDGPUSubtarget::makeLIDRangeMetadata(Instruction *I) const {
560560
else
561561
++MaxSize;
562562

563-
MDBuilder MDB(I->getContext());
564-
MDNode *MaxWorkGroupSizeRange = MDB.createRange(APInt(32, MinSize),
565-
APInt(32, MaxSize));
566-
I->setMetadata(LLVMContext::MD_range, MaxWorkGroupSizeRange);
563+
APInt Lower{32, MinSize};
564+
APInt Upper{32, MaxSize};
565+
if (auto *CI = dyn_cast<CallBase>(I)) {
566+
ConstantRange Range(Lower, Upper);
567+
CI->addRangeRetAttr(Range);
568+
} else {
569+
MDBuilder MDB(I->getContext());
570+
MDNode *MaxWorkGroupSizeRange = MDB.createRange(Lower, Upper);
571+
I->setMetadata(LLVMContext::MD_range, MaxWorkGroupSizeRange);
572+
}
567573
return true;
568574
}
569575

‎llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll

Lines changed: 8 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -52,9 +52,9 @@
5252
; HSAOPT: [[LDZU:%[0-9]+]] = load i32, ptr addrspace(4) [[GEP1]], align 4, !range !2, !invariant.load !1
5353
; HSAOPT: [[EXTRACTY:%[0-9]+]] = lshr i32 [[LDXY]], 16
5454

55-
; HSAOPT: [[WORKITEM_ID_X:%[0-9]+]] = call i32 @llvm.amdgcn.workitem.id.x(), !range !3
56-
; HSAOPT: [[WORKITEM_ID_Y:%[0-9]+]] = call i32 @llvm.amdgcn.workitem.id.y(), !range !3
57-
; HSAOPT: [[WORKITEM_ID_Z:%[0-9]+]] = call i32 @llvm.amdgcn.workitem.id.z(), !range !3
55+
; HSAOPT: [[WORKITEM_ID_X:%[0-9]+]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.x()
56+
; HSAOPT: [[WORKITEM_ID_Y:%[0-9]+]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.y()
57+
; HSAOPT: [[WORKITEM_ID_Z:%[0-9]+]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.z()
5858

5959
; HSAOPT: [[Y_SIZE_X_Z_SIZE:%[0-9]+]] = mul nuw nsw i32 [[EXTRACTY]], [[LDZU]]
6060
; HSAOPT: [[YZ_X_XID:%[0-9]+]] = mul i32 [[Y_SIZE_X_Z_SIZE]], [[WORKITEM_ID_X]]
@@ -68,11 +68,11 @@
6868
; HSAOPT: %arrayidx12 = getelementptr inbounds [5 x i32], ptr addrspace(3) [[LOCAL_GEP]], i32 0, i32 1
6969

7070

71-
; NOHSAOPT: call i32 @llvm.r600.read.local.size.y(), !range !1
72-
; NOHSAOPT: call i32 @llvm.r600.read.local.size.z(), !range !1
73-
; NOHSAOPT: call i32 @llvm.amdgcn.workitem.id.x(), !range !2
74-
; NOHSAOPT: call i32 @llvm.amdgcn.workitem.id.y(), !range !2
75-
; NOHSAOPT: call i32 @llvm.amdgcn.workitem.id.z(), !range !2
71+
; NOHSAOPT: call range(i32 0, 257) i32 @llvm.r600.read.local.size.y()
72+
; NOHSAOPT: call range(i32 0, 257) i32 @llvm.r600.read.local.size.z()
73+
; NOHSAOPT: call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.x()
74+
; NOHSAOPT: call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.y()
75+
; NOHSAOPT: call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.z()
7676
define amdgpu_kernel void @mova_same_clause(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in) #0 {
7777
entry:
7878
%stack = alloca [5 x i32], align 4, addrspace(5)
@@ -533,8 +533,3 @@ attributes #1 = { nounwind "amdgpu-flat-work-group-size"="1,256" }
533533
!99 = !{i32 1, !"amdhsa_code_object_version", i32 400}
534534

535535
; HSAOPT: !1 = !{}
536-
; HSAOPT: !2 = !{i32 0, i32 257}
537-
; HSAOPT: !3 = !{i32 0, i32 256}
538-
539-
; NOHSAOPT: !1 = !{i32 0, i32 257}
540-
; NOHSAOPT: !2 = !{i32 0, i32 256}

‎llvm/test/CodeGen/AMDGPU/private-memory-r600.ll

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -12,11 +12,11 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone
1212
; R600: LDS_READ
1313
; R600: LDS_READ
1414

15-
; OPT: call i32 @llvm.r600.read.local.size.y(), !range !0
16-
; OPT: call i32 @llvm.r600.read.local.size.z(), !range !0
17-
; OPT: call i32 @llvm.r600.read.tidig.x(), !range !1
18-
; OPT: call i32 @llvm.r600.read.tidig.y(), !range !1
19-
; OPT: call i32 @llvm.r600.read.tidig.z(), !range !1
15+
; OPT: call range(i32 0, 257) i32 @llvm.r600.read.local.size.y()
16+
; OPT: call range(i32 0, 257) i32 @llvm.r600.read.local.size.z()
17+
; OPT: call range(i32 0, 256) i32 @llvm.r600.read.tidig.x()
18+
; OPT: call range(i32 0, 256) i32 @llvm.r600.read.tidig.y()
19+
; OPT: call range(i32 0, 256) i32 @llvm.r600.read.tidig.z()
2020

2121
define amdgpu_kernel void @mova_same_clause(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in) #0 {
2222
entry:
@@ -276,7 +276,4 @@ define amdgpu_kernel void @ptrtoint(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
276276
ret void
277277
}
278278

279-
; OPT: !0 = !{i32 0, i32 257}
280-
; OPT: !1 = !{i32 0, i32 256}
281-
282279
attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,2" "amdgpu-flat-work-group-size"="1,256" }

‎llvm/test/CodeGen/AMDGPU/promote-alloca-strip-abi-opt-attributes.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,9 @@
55

66
; CHECK-LABEL: define amdgpu_kernel void @promote_to_lds(ptr addrspace(1) %out, i32 %in) #0 {
77
; CHECK: call noalias nonnull dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
8-
; CHECK: call i32 @llvm.amdgcn.workitem.id.x(), !range !2
9-
; CHECK: call i32 @llvm.amdgcn.workitem.id.y(), !range !2
10-
; CHECK: call i32 @llvm.amdgcn.workitem.id.z(), !range !2
8+
; CHECK: call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.x()
9+
; CHECK: call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.y()
10+
; CHECK: call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.z()
1111
define amdgpu_kernel void @promote_to_lds(ptr addrspace(1) %out, i32 %in) #0 {
1212
entry:
1313
%tmp = alloca [2 x i32], addrspace(5)

‎llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll

Lines changed: 46 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -8,22 +8,22 @@
88
define amdgpu_kernel void @lds_promoted_alloca_icmp_same_derived_pointer(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
99
; CHECK-LABEL: @lds_promoted_alloca_icmp_same_derived_pointer(
1010
; CHECK-NEXT: [[TMP1:%.*]] = call noalias nonnull dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
11-
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr addrspace(4) [[TMP1]], i64 1
12-
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(4) [[TMP3]], align 4, !invariant.load !0
13-
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr addrspace(4) [[TMP1]], i64 2
14-
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(4) [[TMP5]], align 4, !range [[RNG1:![0-9]+]], !invariant.load !0
15-
; CHECK-NEXT: [[TMP7:%.*]] = lshr i32 [[TMP4]], 16
16-
; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.workitem.id.x(), !range [[RNG2:![0-9]+]]
17-
; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.amdgcn.workitem.id.y(), !range [[RNG2]]
18-
; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.workitem.id.z(), !range [[RNG2]]
19-
; CHECK-NEXT: [[TMP11:%.*]] = mul nuw nsw i32 [[TMP7]], [[TMP6]]
20-
; CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], [[TMP8]]
21-
; CHECK-NEXT: [[TMP13:%.*]] = mul nuw nsw i32 [[TMP9]], [[TMP6]]
22-
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]]
23-
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP14]], [[TMP10]]
24-
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [256 x [16 x i32]], ptr addrspace(3) @lds_promoted_alloca_icmp_same_derived_pointer.alloca, i32 0, i32 [[TMP15]]
25-
; CHECK-NEXT: [[PTR0:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(3) [[TMP16]], i32 0, i32 [[A:%.*]]
26-
; CHECK-NEXT: [[PTR1:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(3) [[TMP16]], i32 0, i32 [[B:%.*]]
11+
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr addrspace(4) [[TMP1]], i64 1
12+
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[TMP2]], align 4, !invariant.load [[META0:![0-9]+]]
13+
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr addrspace(4) [[TMP1]], i64 2
14+
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(4) [[TMP4]], align 4, !range [[RNG1:![0-9]+]], !invariant.load [[META0]]
15+
; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP3]], 16
16+
; CHECK-NEXT: [[TMP7:%.*]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.x()
17+
; CHECK-NEXT: [[TMP8:%.*]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.y()
18+
; CHECK-NEXT: [[TMP9:%.*]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.z()
19+
; CHECK-NEXT: [[TMP10:%.*]] = mul nuw nsw i32 [[TMP6]], [[TMP5]]
20+
; CHECK-NEXT: [[TMP11:%.*]] = mul i32 [[TMP10]], [[TMP7]]
21+
; CHECK-NEXT: [[TMP12:%.*]] = mul nuw nsw i32 [[TMP8]], [[TMP5]]
22+
; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP11]], [[TMP12]]
23+
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], [[TMP9]]
24+
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [256 x [16 x i32]], ptr addrspace(3) @lds_promoted_alloca_icmp_same_derived_pointer.alloca, i32 0, i32 [[TMP14]]
25+
; CHECK-NEXT: [[PTR0:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(3) [[TMP15]], i32 0, i32 [[A:%.*]]
26+
; CHECK-NEXT: [[PTR1:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(3) [[TMP15]], i32 0, i32 [[B:%.*]]
2727
; CHECK-NEXT: [[CMP:%.*]] = icmp eq ptr addrspace(3) [[PTR0]], [[PTR1]]
2828
; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32
2929
; CHECK-NEXT: store volatile i32 [[ZEXT]], ptr addrspace(1) [[OUT:%.*]], align 4
@@ -50,21 +50,21 @@ define amdgpu_kernel void @lds_promoted_alloca_icmp_same_derived_pointer(ptr add
5050
define amdgpu_kernel void @lds_promoted_alloca_icmp_null_rhs(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
5151
; CHECK-LABEL: @lds_promoted_alloca_icmp_null_rhs(
5252
; CHECK-NEXT: [[TMP1:%.*]] = call noalias nonnull dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
53-
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr addrspace(4) [[TMP1]], i64 1
54-
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(4) [[TMP3]], align 4, !invariant.load !0
55-
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr addrspace(4) [[TMP1]], i64 2
56-
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(4) [[TMP5]], align 4, !range [[RNG1]], !invariant.load !0
57-
; CHECK-NEXT: [[TMP7:%.*]] = lshr i32 [[TMP4]], 16
58-
; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.workitem.id.x(), !range [[RNG2]]
59-
; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.amdgcn.workitem.id.y(), !range [[RNG2]]
60-
; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.workitem.id.z(), !range [[RNG2]]
61-
; CHECK-NEXT: [[TMP11:%.*]] = mul nuw nsw i32 [[TMP7]], [[TMP6]]
62-
; CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], [[TMP8]]
63-
; CHECK-NEXT: [[TMP13:%.*]] = mul nuw nsw i32 [[TMP9]], [[TMP6]]
64-
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]]
65-
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP14]], [[TMP10]]
66-
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [256 x [16 x i32]], ptr addrspace(3) @lds_promoted_alloca_icmp_null_rhs.alloca, i32 0, i32 [[TMP15]]
67-
; CHECK-NEXT: [[PTR0:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(3) [[TMP16]], i32 0, i32 [[A:%.*]]
53+
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr addrspace(4) [[TMP1]], i64 1
54+
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[TMP2]], align 4, !invariant.load [[META0]]
55+
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr addrspace(4) [[TMP1]], i64 2
56+
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(4) [[TMP4]], align 4, !range [[RNG1]], !invariant.load [[META0]]
57+
; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP3]], 16
58+
; CHECK-NEXT: [[TMP7:%.*]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.x()
59+
; CHECK-NEXT: [[TMP8:%.*]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.y()
60+
; CHECK-NEXT: [[TMP9:%.*]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.z()
61+
; CHECK-NEXT: [[TMP10:%.*]] = mul nuw nsw i32 [[TMP6]], [[TMP5]]
62+
; CHECK-NEXT: [[TMP11:%.*]] = mul i32 [[TMP10]], [[TMP7]]
63+
; CHECK-NEXT: [[TMP12:%.*]] = mul nuw nsw i32 [[TMP8]], [[TMP5]]
64+
; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP11]], [[TMP12]]
65+
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], [[TMP9]]
66+
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [256 x [16 x i32]], ptr addrspace(3) @lds_promoted_alloca_icmp_null_rhs.alloca, i32 0, i32 [[TMP14]]
67+
; CHECK-NEXT: [[PTR0:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(3) [[TMP15]], i32 0, i32 [[A:%.*]]
6868
; CHECK-NEXT: [[CMP:%.*]] = icmp eq ptr addrspace(3) [[PTR0]], null
6969
; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32
7070
; CHECK-NEXT: store volatile i32 [[ZEXT]], ptr addrspace(1) [[OUT:%.*]], align 4
@@ -89,21 +89,21 @@ define amdgpu_kernel void @lds_promoted_alloca_icmp_null_rhs(ptr addrspace(1) %o
8989
define amdgpu_kernel void @lds_promoted_alloca_icmp_null_lhs(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
9090
; CHECK-LABEL: @lds_promoted_alloca_icmp_null_lhs(
9191
; CHECK-NEXT: [[TMP1:%.*]] = call noalias nonnull dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
92-
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr addrspace(4) [[TMP1]], i64 1
93-
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(4) [[TMP3]], align 4, !invariant.load !0
94-
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr addrspace(4) [[TMP1]], i64 2
95-
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(4) [[TMP5]], align 4, !range [[RNG1]], !invariant.load !0
96-
; CHECK-NEXT: [[TMP7:%.*]] = lshr i32 [[TMP4]], 16
97-
; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.workitem.id.x(), !range [[RNG2]]
98-
; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.amdgcn.workitem.id.y(), !range [[RNG2]]
99-
; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.workitem.id.z(), !range [[RNG2]]
100-
; CHECK-NEXT: [[TMP11:%.*]] = mul nuw nsw i32 [[TMP7]], [[TMP6]]
101-
; CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], [[TMP8]]
102-
; CHECK-NEXT: [[TMP13:%.*]] = mul nuw nsw i32 [[TMP9]], [[TMP6]]
103-
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]]
104-
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP14]], [[TMP10]]
105-
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [256 x [16 x i32]], ptr addrspace(3) @lds_promoted_alloca_icmp_null_lhs.alloca, i32 0, i32 [[TMP15]]
106-
; CHECK-NEXT: [[PTR0:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(3) [[TMP16]], i32 0, i32 [[A:%.*]]
92+
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr addrspace(4) [[TMP1]], i64 1
93+
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[TMP2]], align 4, !invariant.load [[META0]]
94+
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr addrspace(4) [[TMP1]], i64 2
95+
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(4) [[TMP4]], align 4, !range [[RNG1]], !invariant.load [[META0]]
96+
; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP3]], 16
97+
; CHECK-NEXT: [[TMP7:%.*]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.x()
98+
; CHECK-NEXT: [[TMP8:%.*]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.y()
99+
; CHECK-NEXT: [[TMP9:%.*]] = call range(i32 0, 256) i32 @llvm.amdgcn.workitem.id.z()
100+
; CHECK-NEXT: [[TMP10:%.*]] = mul nuw nsw i32 [[TMP6]], [[TMP5]]
101+
; CHECK-NEXT: [[TMP11:%.*]] = mul i32 [[TMP10]], [[TMP7]]
102+
; CHECK-NEXT: [[TMP12:%.*]] = mul nuw nsw i32 [[TMP8]], [[TMP5]]
103+
; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP11]], [[TMP12]]
104+
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], [[TMP9]]
105+
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [256 x [16 x i32]], ptr addrspace(3) @lds_promoted_alloca_icmp_null_lhs.alloca, i32 0, i32 [[TMP14]]
106+
; CHECK-NEXT: [[PTR0:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(3) [[TMP15]], i32 0, i32 [[A:%.*]]
107107
; CHECK-NEXT: [[CMP:%.*]] = icmp eq ptr addrspace(3) null, [[PTR0]]
108108
; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32
109109
; CHECK-NEXT: store volatile i32 [[ZEXT]], ptr addrspace(1) [[OUT:%.*]], align 4

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