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[InstCombine] Introduce tests for D153963
Introduce test cases for folding binops of `select` and cast of the `select` condition. Differential Revision: https://reviews.llvm.org/D155510
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‎llvm/test/Transforms/InstCombine/binop-select-cast-of-select-cond.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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define i64 @add_select_zext(i1 %c) {
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; CHECK-LABEL: define i64 @add_select_zext
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; CHECK-SAME: (i1 [[C:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i64 64, i64 1
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; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[C]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i64 [[SEL]], [[EXT]]
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; CHECK-NEXT: ret i64 [[ADD]]
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;
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%sel = select i1 %c, i64 64, i64 1
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%ext = zext i1 %c to i64
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%add = add i64 %sel, %ext
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ret i64 %add
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}
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define i64 @add_select_sext(i1 %c) {
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; CHECK-LABEL: define i64 @add_select_sext
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; CHECK-SAME: (i1 [[C:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i64 64, i64 1
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; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[C]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SEL]], [[EXT]]
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; CHECK-NEXT: ret i64 [[ADD]]
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;
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%sel = select i1 %c, i64 64, i64 1
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%ext = sext i1 %c to i64
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%add = add i64 %sel, %ext
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ret i64 %add
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}
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define i64 @add_select_not_zext(i1 %c) {
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; CHECK-LABEL: define i64 @add_select_not_zext
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; CHECK-SAME: (i1 [[C:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i64 64, i64 1
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; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C]], true
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; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[NOT_C]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i64 [[SEL]], [[EXT]]
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; CHECK-NEXT: ret i64 [[ADD]]
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;
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%sel = select i1 %c, i64 64, i64 1
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%not.c = xor i1 %c, true
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%ext = zext i1 %not.c to i64
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%add = add i64 %sel, %ext
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ret i64 %add
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}
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define i64 @add_select_not_sext(i1 %c) {
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; CHECK-LABEL: define i64 @add_select_not_sext
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; CHECK-SAME: (i1 [[C:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i64 64, i64 1
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; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C]], true
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; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[NOT_C]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SEL]], [[EXT]]
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; CHECK-NEXT: ret i64 [[ADD]]
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;
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%sel = select i1 %c, i64 64, i64 1
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%not.c = xor i1 %c, true
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%ext = sext i1 %not.c to i64
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%add = add i64 %sel, %ext
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ret i64 %add
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}
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define i64 @sub_select_sext(i1 %c, i64 %arg) {
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; CHECK-LABEL: define i64 @sub_select_sext
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; CHECK-SAME: (i1 [[C:%.*]], i64 [[ARG:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i64 64, i64 [[ARG]]
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; CHECK-NEXT: [[EXT_NEG:%.*]] = zext i1 [[C]] to i64
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; CHECK-NEXT: [[SUB:%.*]] = add i64 [[SEL]], [[EXT_NEG]]
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; CHECK-NEXT: ret i64 [[SUB]]
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;
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%sel = select i1 %c, i64 64, i64 %arg
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%ext = sext i1 %c to i64
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%sub = sub i64 %sel, %ext
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ret i64 %sub
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}
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define i64 @sub_select_not_zext(i1 %c, i64 %arg) {
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; CHECK-LABEL: define i64 @sub_select_not_zext
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; CHECK-SAME: (i1 [[C:%.*]], i64 [[ARG:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i64 [[ARG]], i64 64
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; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C]], true
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; CHECK-NEXT: [[EXT_NEG:%.*]] = sext i1 [[NOT_C]] to i64
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; CHECK-NEXT: [[SUB:%.*]] = add i64 [[SEL]], [[EXT_NEG]]
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; CHECK-NEXT: ret i64 [[SUB]]
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;
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%sel = select i1 %c, i64 %arg, i64 64
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%not.c = xor i1 %c, true
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%ext = zext i1 %not.c to i64
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%sub = sub i64 %sel, %ext
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ret i64 %sub
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}
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define i64 @sub_select_not_sext(i1 %c, i64 %arg) {
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; CHECK-LABEL: define i64 @sub_select_not_sext
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; CHECK-SAME: (i1 [[C:%.*]], i64 [[ARG:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i64 [[ARG]], i64 64
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; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C]], true
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; CHECK-NEXT: [[EXT_NEG:%.*]] = zext i1 [[NOT_C]] to i64
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; CHECK-NEXT: [[SUB:%.*]] = add i64 [[SEL]], [[EXT_NEG]]
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; CHECK-NEXT: ret i64 [[SUB]]
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;
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%sel = select i1 %c, i64 %arg, i64 64
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%not.c = xor i1 %c, true
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%ext = sext i1 %not.c to i64
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%sub = sub i64 %sel, %ext
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ret i64 %sub
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}
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define i64 @mul_select_zext(i1 %c, i64 %arg) {
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; CHECK-LABEL: define i64 @mul_select_zext
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; CHECK-SAME: (i1 [[C:%.*]], i64 [[ARG:%.*]]) {
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; CHECK-NEXT: [[MUL:%.*]] = select i1 [[C]], i64 [[ARG]], i64 0
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; CHECK-NEXT: ret i64 [[MUL]]
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;
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%sel = select i1 %c, i64 %arg, i64 1
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%ext = zext i1 %c to i64
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%mul = mul i64 %sel, %ext
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ret i64 %mul
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}
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define i64 @mul_select_sext(i1 %c) {
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; CHECK-LABEL: define i64 @mul_select_sext
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; CHECK-SAME: (i1 [[C:%.*]]) {
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; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[C]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C]], i64 6, i64 0
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; CHECK-NEXT: [[MUL:%.*]] = shl i64 [[EXT]], [[TMP1]]
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; CHECK-NEXT: ret i64 [[MUL]]
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;
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%sel = select i1 %c, i64 64, i64 1
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%ext = sext i1 %c to i64
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%mul = mul i64 %sel, %ext
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ret i64 %mul
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}
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define i64 @select_zext_different_condition(i1 %c, i1 %d) {
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; CHECK-LABEL: define i64 @select_zext_different_condition
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; CHECK-SAME: (i1 [[C:%.*]], i1 [[D:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i64 64, i64 1
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; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[D]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i64 [[SEL]], [[EXT]]
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; CHECK-NEXT: ret i64 [[ADD]]
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;
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%sel = select i1 %c, i64 64, i64 1
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%ext = zext i1 %d to i64
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%add = add i64 %sel, %ext
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ret i64 %add
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}
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define <2 x i64> @vector_test(i1 %c) {
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; CHECK-LABEL: define <2 x i64> @vector_test
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; CHECK-SAME: (i1 [[C:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], <2 x i64> <i64 64, i64 64>, <2 x i64> <i64 1, i64 1>
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; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[C]] to i64
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; CHECK-NEXT: [[VEC0:%.*]] = insertelement <2 x i64> undef, i64 [[EXT]], i64 0
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; CHECK-NEXT: [[VEC1:%.*]] = shufflevector <2 x i64> [[VEC0]], <2 x i64> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw <2 x i64> [[SEL]], [[VEC1]]
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; CHECK-NEXT: ret <2 x i64> [[ADD]]
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;
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%sel = select i1 %c, <2 x i64> <i64 64, i64 64>, <2 x i64> <i64 1, i64 1>
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%ext = zext i1 %c to i64
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%vec0 = insertelement <2 x i64> undef, i64 %ext, i32 0
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%vec1 = insertelement <2 x i64> %vec0, i64 %ext, i32 1
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%add = add <2 x i64> %sel, %vec1
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ret <2 x i64> %add
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}
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define i64 @multiuse_add(i1 %c) {
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; CHECK-LABEL: define i64 @multiuse_add
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; CHECK-SAME: (i1 [[C:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i64 64, i64 1
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; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[C]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i64 [[SEL]], [[EXT]]
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; CHECK-NEXT: [[ADD2:%.*]] = add nuw nsw i64 [[ADD]], 1
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; CHECK-NEXT: ret i64 [[ADD2]]
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;
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%sel = select i1 %c, i64 64, i64 1
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%ext = zext i1 %c to i64
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%add = add i64 %sel, %ext
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%add2 = add i64 %add, 1
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ret i64 %add2
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}
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define i64 @multiuse_select(i1 %c) {
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; CHECK-LABEL: define i64 @multiuse_select
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; CHECK-SAME: (i1 [[C:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i64 64, i64 0
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; CHECK-NEXT: [[EXT_NEG:%.*]] = sext i1 [[C]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SEL]], [[EXT_NEG]]
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i64 [[SEL]], [[ADD]]
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; CHECK-NEXT: ret i64 [[MUL]]
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;
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%sel = select i1 %c, i64 64, i64 0
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%ext = zext i1 %c to i64
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%add = sub i64 %sel, %ext
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%mul = mul i64 %sel, %add
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ret i64 %mul
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}
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define i64 @select_non_const_sides(i1 %c, i64 %arg1, i64 %arg2) {
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; CHECK-LABEL: define i64 @select_non_const_sides
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; CHECK-SAME: (i1 [[C:%.*]], i64 [[ARG1:%.*]], i64 [[ARG2:%.*]]) {
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; CHECK-NEXT: [[EXT_NEG:%.*]] = sext i1 [[C]] to i64
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i64 [[ARG1]], i64 [[ARG2]]
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; CHECK-NEXT: [[SUB:%.*]] = add i64 [[SEL]], [[EXT_NEG]]
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; CHECK-NEXT: ret i64 [[SUB]]
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;
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%ext = zext i1 %c to i64
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%sel = select i1 %c, i64 %arg1, i64 %arg2
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%sub = sub i64 %sel, %ext
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ret i64 %sub
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}
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define i6 @sub_select_sext_op_swapped_non_const_args(i1 %c, i6 %argT, i6 %argF) {
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; CHECK-LABEL: define i6 @sub_select_sext_op_swapped_non_const_args
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; CHECK-SAME: (i1 [[C:%.*]], i6 [[ARGT:%.*]], i6 [[ARGF:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i6 [[ARGT]], i6 [[ARGF]]
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; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[C]] to i6
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; CHECK-NEXT: [[SUB:%.*]] = sub i6 [[EXT]], [[SEL]]
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; CHECK-NEXT: ret i6 [[SUB]]
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;
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%sel = select i1 %c, i6 %argT, i6 %argF
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%ext = sext i1 %c to i6
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%sub = sub i6 %ext, %sel
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ret i6 %sub
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}
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define i6 @sub_select_zext_op_swapped_non_const_args(i1 %c, i6 %argT, i6 %argF) {
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; CHECK-LABEL: define i6 @sub_select_zext_op_swapped_non_const_args
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; CHECK-SAME: (i1 [[C:%.*]], i6 [[ARGT:%.*]], i6 [[ARGF:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i6 [[ARGT]], i6 [[ARGF]]
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; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[C]] to i6
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; CHECK-NEXT: [[SUB:%.*]] = sub i6 [[EXT]], [[SEL]]
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; CHECK-NEXT: ret i6 [[SUB]]
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;
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%sel = select i1 %c, i6 %argT, i6 %argF
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%ext = zext i1 %c to i6
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%sub = sub i6 %ext, %sel
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ret i6 %sub
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}

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