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Handle index>256 cases (except for LMUL==8 case)
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+44
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lines changed

2 files changed

+44
-1
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,7 @@
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#include "llvm/Support/KnownBits.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TargetParser/RISCVTargetParser.h"
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#include <optional>
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using namespace llvm;
@@ -10768,9 +10769,20 @@ SDValue RISCVTargetLowering::lowerMaskedLoad(SDValue Op,
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if (ContainerVT.isFloatingPoint())
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IndexVT = IndexVT.changeVectorElementTypeToInteger();
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10771-
if (Subtarget.isRV32() && IndexVT.getVectorElementType().bitsGT(XLenVT))
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MVT IndexEltVT = IndexVT.getVectorElementType();
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if (Subtarget.isRV32() && IndexEltVT.bitsGT(XLenVT))
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IndexVT = IndexVT.changeVectorElementType(XLenVT);
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// If index vector is an i8 vector and the element count exceeds 256, we
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// should change the element type of index vector to i16 to avoid overflow.
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if (IndexEltVT == MVT::i8 &&
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VT.getVectorElementCount().getKnownMinValue() > 256) {
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// FIXME: Don't know how to make LMUL==8 case legal.
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assert(getLMUL(IndexVT) != RISCVII::LMUL_8 &&
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"We don't know how to lower LMUL==8 case");
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IndexVT = IndexVT.changeVectorElementType(MVT::i16);
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}
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Index = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
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DAG.getConstant(Intrinsic::riscv_viota, DL, XLenVT),
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DAG.getUNDEF(IndexVT), Mask, VL);

llvm/test/CodeGen/RISCV/rvv/expandload.ll

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1547,3 +1547,34 @@ declare <4 x i64> @llvm.masked.expandload.v4i64(ptr, <4 x i1>, <4 x i64>)
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declare <8 x i64> @llvm.masked.expandload.v8i64(ptr, <8 x i1>, <8 x i64>)
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declare <16 x i64> @llvm.masked.expandload.v16i64(ptr, <16 x i1>, <16 x i64>)
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declare <32 x i64> @llvm.masked.expandload.v32i64(ptr, <32 x i1>, <32 x i64>)
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define <512 x i8> @test_expandload_v512i8(ptr %base, <512 x i1> %mask, <512 x i8> %passthru) "target-features"="+zvl1024b" {
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; RV64-LABEL: test_expandload_v512i8:
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; RV64: # %bb.0:
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; RV64-NEXT: li a1, 512
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; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, ma
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; RV64-NEXT: viota.m v16, v0
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; RV64-NEXT: vsetvli zero, zero, e8, m4, ta, mu
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; RV64-NEXT: vluxei16.v v8, (a0), v16, v0.t
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; RV64-NEXT: ret
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;
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; RV32-LABEL: test_expandload_v512i8:
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; RV32: # %bb.0:
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; RV32-NEXT: li a1, 512
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; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, ma
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; RV32-NEXT: viota.m v16, v0
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; RV32-NEXT: vsetvli zero, zero, e8, m4, ta, mu
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; RV32-NEXT: vluxei16.v v8, (a0), v16, v0.t
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; RV32-NEXT: ret
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%res = call <512 x i8> @llvm.masked.expandload.v512i8(ptr align 1 %base, <512 x i1> %mask, <512 x i8> %passthru)
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ret <512 x i8> %res
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}
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; FIXME: Don't know how to make it legal.
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; define <1024 x i8> @test_expandload_v1024i8(ptr %base, <1024 x i1> %mask, <1024 x i8> %passthru) "target-features"="+zvl1024b" {
1575+
; %res = call <1024 x i8> @llvm.masked.expandload.v1024i8(ptr align 1 %base, <1024 x i1> %mask, <1024 x i8> %passthru)
1576+
; ret <1024 x i8> %res
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; }
1578+
1579+
declare <512 x i8> @llvm.masked.expandload.v512i8(ptr, <512 x i1>, <512 x i8>)
1580+
declare <1024 x i8> @llvm.masked.expandload.v1024i8(ptr, <1024 x i1>, <1024 x i8>)

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