@@ -1547,3 +1547,34 @@ declare <4 x i64> @llvm.masked.expandload.v4i64(ptr, <4 x i1>, <4 x i64>)
1547
1547
declare <8 x i64 > @llvm.masked.expandload.v8i64 (ptr , <8 x i1 >, <8 x i64 >)
1548
1548
declare <16 x i64 > @llvm.masked.expandload.v16i64 (ptr , <16 x i1 >, <16 x i64 >)
1549
1549
declare <32 x i64 > @llvm.masked.expandload.v32i64 (ptr , <32 x i1 >, <32 x i64 >)
1550
+
1551
+ define <512 x i8 > @test_expandload_v512i8 (ptr %base , <512 x i1 > %mask , <512 x i8 > %passthru ) "target-features" ="+zvl1024b" {
1552
+ ; RV64-LABEL: test_expandload_v512i8:
1553
+ ; RV64: # %bb.0:
1554
+ ; RV64-NEXT: li a1, 512
1555
+ ; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, ma
1556
+ ; RV64-NEXT: viota.m v16, v0
1557
+ ; RV64-NEXT: vsetvli zero, zero, e8, m4, ta, mu
1558
+ ; RV64-NEXT: vluxei16.v v8, (a0), v16, v0.t
1559
+ ; RV64-NEXT: ret
1560
+ ;
1561
+ ; RV32-LABEL: test_expandload_v512i8:
1562
+ ; RV32: # %bb.0:
1563
+ ; RV32-NEXT: li a1, 512
1564
+ ; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, ma
1565
+ ; RV32-NEXT: viota.m v16, v0
1566
+ ; RV32-NEXT: vsetvli zero, zero, e8, m4, ta, mu
1567
+ ; RV32-NEXT: vluxei16.v v8, (a0), v16, v0.t
1568
+ ; RV32-NEXT: ret
1569
+ %res = call <512 x i8 > @llvm.masked.expandload.v512i8 (ptr align 1 %base , <512 x i1 > %mask , <512 x i8 > %passthru )
1570
+ ret <512 x i8 > %res
1571
+ }
1572
+
1573
+ ; FIXME: Don't know how to make it legal.
1574
+ ; define <1024 x i8> @test_expandload_v1024i8(ptr %base, <1024 x i1> %mask, <1024 x i8> %passthru) "target-features"="+zvl1024b" {
1575
+ ; %res = call <1024 x i8> @llvm.masked.expandload.v1024i8(ptr align 1 %base, <1024 x i1> %mask, <1024 x i8> %passthru)
1576
+ ; ret <1024 x i8> %res
1577
+ ; }
1578
+
1579
+ declare <512 x i8 > @llvm.masked.expandload.v512i8 (ptr , <512 x i1 >, <512 x i8 >)
1580
+ declare <1024 x i8 > @llvm.masked.expandload.v1024i8 (ptr , <1024 x i1 >, <1024 x i8 >)
0 commit comments