@@ -153,6 +153,7 @@ static const unsigned MaxParallelChains = 64;
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static SDValue getCopyFromPartsVector (SelectionDAG &DAG, const SDLoc &DL,
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const SDValue *Parts, unsigned NumParts,
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MVT PartVT, EVT ValueVT, const Value *V,
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+ SDValue InChain,
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std::optional<CallingConv::ID> CC);
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// / getCopyFromParts - Create a value that contains the specified legal parts
@@ -163,6 +164,7 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
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static SDValue
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getCopyFromParts (SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts,
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unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V,
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+ SDValue InChain,
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std::optional<CallingConv::ID> CC = std::nullopt,
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std::optional<ISD::NodeType> AssertOp = std::nullopt) {
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// Let the target assemble the parts if it wants to
@@ -173,7 +175,7 @@ getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts,
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if (ValueVT.isVector ())
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return getCopyFromPartsVector (DAG, DL, Parts, NumParts, PartVT, ValueVT, V,
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- CC);
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+ InChain, CC);
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assert (NumParts > 0 && " No parts to assemble!" );
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SDValue Val = Parts[0 ];
@@ -194,10 +196,10 @@ getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts,
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EVT HalfVT = EVT::getIntegerVT (*DAG.getContext (), RoundBits/2 );
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if (RoundParts > 2 ) {
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- Lo = getCopyFromParts (DAG, DL, Parts, RoundParts / 2 ,
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- PartVT, HalfVT, V );
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- Hi = getCopyFromParts (DAG, DL, Parts + RoundParts / 2 ,
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- RoundParts / 2 , PartVT, HalfVT, V);
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+ Lo = getCopyFromParts (DAG, DL, Parts, RoundParts / 2 , PartVT, HalfVT, V,
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+ InChain );
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+ Hi = getCopyFromParts (DAG, DL, Parts + RoundParts / 2 , RoundParts / 2 ,
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+ PartVT, HalfVT, V, InChain );
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} else {
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Lo = DAG.getNode (ISD::BITCAST, DL, HalfVT, Parts[0 ]);
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Hi = DAG.getNode (ISD::BITCAST, DL, HalfVT, Parts[1 ]);
@@ -213,7 +215,7 @@ getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts,
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unsigned OddParts = NumParts - RoundParts;
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EVT OddVT = EVT::getIntegerVT (*DAG.getContext (), OddParts * PartBits);
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Hi = getCopyFromParts (DAG, DL, Parts + RoundParts, OddParts, PartVT,
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- OddVT, V, CC);
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+ OddVT, V, InChain, CC);
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// Combine the round and odd parts.
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Lo = Val;
@@ -243,7 +245,8 @@ getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts,
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assert (ValueVT.isFloatingPoint () && PartVT.isInteger () &&
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!PartVT.isVector () && " Unexpected split" );
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EVT IntVT = EVT::getIntegerVT (*DAG.getContext (), ValueVT.getSizeInBits ());
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- Val = getCopyFromParts (DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC);
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+ Val = getCopyFromParts (DAG, DL, Parts, NumParts, PartVT, IntVT, V,
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+ InChain, CC);
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}
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}
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@@ -283,10 +286,20 @@ getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts,
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if (PartEVT.isFloatingPoint () && ValueVT.isFloatingPoint ()) {
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// FP_ROUND's are always exact here.
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- if (ValueVT.bitsLT (Val.getValueType ()))
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- return DAG.getNode (
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- ISD::FP_ROUND, DL, ValueVT, Val,
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- DAG.getTargetConstant (1 , DL, TLI.getPointerTy (DAG.getDataLayout ())));
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+ if (ValueVT.bitsLT (Val.getValueType ())) {
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+
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+ SDValue NoChange =
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+ DAG.getTargetConstant (1 , DL, TLI.getPointerTy (DAG.getDataLayout ()));
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+
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+ if (DAG.getMachineFunction ().getFunction ().getAttributes ().hasFnAttr (
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+ llvm::Attribute::StrictFP)) {
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+ return DAG.getNode (ISD::STRICT_FP_ROUND, DL,
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+ DAG.getVTList (ValueVT, MVT::Other), InChain, Val,
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+ NoChange);
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+ }
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+
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+ return DAG.getNode (ISD::FP_ROUND, DL, ValueVT, Val, NoChange);
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+ }
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return DAG.getNode (ISD::FP_EXTEND, DL, ValueVT, Val);
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}
@@ -324,6 +337,7 @@ static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
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static SDValue getCopyFromPartsVector (SelectionDAG &DAG, const SDLoc &DL,
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const SDValue *Parts, unsigned NumParts,
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MVT PartVT, EVT ValueVT, const Value *V,
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+ SDValue InChain,
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std::optional<CallingConv::ID> CallConv) {
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assert (ValueVT.isVector () && " Not a vector value" );
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assert (NumParts > 0 && " No parts to assemble!" );
@@ -362,17 +376,17 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
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// If the register was not expanded, truncate or copy the value,
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// as appropriate.
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for (unsigned i = 0 ; i != NumParts; ++i)
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- Ops[i] = getCopyFromParts (DAG, DL, &Parts[i], 1 ,
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- PartVT, IntermediateVT, V , CallConv);
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+ Ops[i] = getCopyFromParts (DAG, DL, &Parts[i], 1 , PartVT, IntermediateVT,
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+ V, InChain , CallConv);
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} else if (NumParts > 0 ) {
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// If the intermediate type was expanded, build the intermediate
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// operands from the parts.
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assert (NumParts % NumIntermediates == 0 &&
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" Must expand into a divisible number of parts!" );
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unsigned Factor = NumParts / NumIntermediates;
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for (unsigned i = 0 ; i != NumIntermediates; ++i)
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- Ops[i] = getCopyFromParts (DAG, DL, &Parts[i * Factor], Factor,
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- PartVT, IntermediateVT, V, CallConv);
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+ Ops[i] = getCopyFromParts (DAG, DL, &Parts[i * Factor], Factor, PartVT,
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+ IntermediateVT, V, InChain , CallConv);
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}
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// Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
@@ -926,7 +940,7 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
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}
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Values[Value] = getCopyFromParts (DAG, dl, Parts.begin (), NumRegs,
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- RegisterVT, ValueVT, V, CallConv);
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+ RegisterVT, ValueVT, V, Chain, CallConv);
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Part += NumRegs;
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Parts.clear ();
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}
@@ -10641,9 +10655,9 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
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unsigned NumRegs = getNumRegistersForCallingConv (CLI.RetTy ->getContext (),
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CLI.CallConv , VT);
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- ReturnValues.push_back (getCopyFromParts (CLI. DAG , CLI. DL , &InVals[CurReg],
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- NumRegs, RegisterVT, VT, nullptr ,
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- CLI.CallConv , AssertOp));
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+ ReturnValues.push_back (getCopyFromParts (
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+ CLI. DAG , CLI. DL , &InVals[CurReg], NumRegs, RegisterVT, VT, nullptr ,
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+ CLI. Chain , CLI.CallConv , AssertOp));
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CurReg += NumRegs;
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}
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@@ -11122,8 +11136,9 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
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MVT VT = ValueVTs[0 ].getSimpleVT ();
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MVT RegVT = TLI->getRegisterType (*CurDAG->getContext (), VT);
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std::optional<ISD::NodeType> AssertOp;
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- SDValue ArgValue = getCopyFromParts (DAG, dl, &InVals[0 ], 1 , RegVT, VT,
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- nullptr , F.getCallingConv (), AssertOp);
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+ SDValue ArgValue =
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+ getCopyFromParts (DAG, dl, &InVals[0 ], 1 , RegVT, VT, nullptr , NewRoot,
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+ F.getCallingConv (), AssertOp);
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MachineFunction& MF = SDB->DAG .getMachineFunction ();
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MachineRegisterInfo& RegInfo = MF.getRegInfo ();
@@ -11195,7 +11210,7 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
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AssertOp = ISD::AssertZext;
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ArgValues.push_back (getCopyFromParts (DAG, dl, &InVals[i], NumParts,
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- PartVT, VT, nullptr ,
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+ PartVT, VT, nullptr , NewRoot,
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F.getCallingConv (), AssertOp));
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}
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