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[X86] Support MOVRS and AVX10.2 instructions. (#113274)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
1 parent c03d09c commit c4248fa

30 files changed

+1593
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lines changed

‎clang/docs/ReleaseNotes.rst

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@@ -624,6 +624,9 @@ X86 Support
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- All intrinsics in tbmintrin.h can now be used in constant expressions.
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- Supported intrinsics for ``MOVRS AND AVX10.2``.
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* Supported intrinsics of ``_mm(256|512)_(mask(z))_loadrs_epi(8|16|32|64)``.
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Arm and AArch64 Support
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^^^^^^^^^^^^^^^^^^^^^^^
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‎clang/include/clang/Basic/BuiltinsX86_64.def

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@@ -161,6 +161,20 @@ TARGET_BUILTIN(__builtin_ia32_aand64, "vv*SOi", "n", "raoint")
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TARGET_BUILTIN(__builtin_ia32_aor64, "vv*SOi", "n", "raoint")
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TARGET_BUILTIN(__builtin_ia32_axor64, "vv*SOi", "n", "raoint")
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164+
// MOVRS and AVX10.2
165+
TARGET_BUILTIN(__builtin_ia32_vmovrsb128, "V16cV16cC*", "nV:128:", "movrs,avx10.2-256")
166+
TARGET_BUILTIN(__builtin_ia32_vmovrsb256, "V32cV32cC*", "nV:256:", "movrs,avx10.2-256")
167+
TARGET_BUILTIN(__builtin_ia32_vmovrsb512, "V64cV64cC*", "nV:512:", "movrs,avx10.2-512")
168+
TARGET_BUILTIN(__builtin_ia32_vmovrsd128, "V4iV4iC*", "nV:128:", "movrs,avx10.2-256")
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TARGET_BUILTIN(__builtin_ia32_vmovrsd256, "V8iV8iC*", "nV:256:", "movrs,avx10.2-256")
170+
TARGET_BUILTIN(__builtin_ia32_vmovrsd512, "V16iV16iC*", "nV:512:", "movrs,avx10.2-512")
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TARGET_BUILTIN(__builtin_ia32_vmovrsq128, "V2OiV2OiC*", "nV:128:", "movrs,avx10.2-256")
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TARGET_BUILTIN(__builtin_ia32_vmovrsq256, "V4OiV4OiC*", "nV:256:", "movrs,avx10.2-256")
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TARGET_BUILTIN(__builtin_ia32_vmovrsq512, "V8OiV8OiC*", "nV:512:", "movrs,avx10.2-512")
174+
TARGET_BUILTIN(__builtin_ia32_vmovrsw128, "V8sV8sC*", "nV:128:", "movrs,avx10.2-256")
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TARGET_BUILTIN(__builtin_ia32_vmovrsw256, "V16sV16sC*", "nV:256:", "movrs,avx10.2-256")
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TARGET_BUILTIN(__builtin_ia32_vmovrsw512, "V32sV32sC*", "nV:512:", "movrs,avx10.2-512")
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164178
#undef BUILTIN
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#undef TARGET_BUILTIN
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#undef TARGET_HEADER_BUILTIN

‎clang/include/clang/Driver/Options.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6424,6 +6424,8 @@ def mmovdiri : Flag<["-"], "mmovdiri">, Group<m_x86_Features_Group>;
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def mno_movdiri : Flag<["-"], "mno-movdiri">, Group<m_x86_Features_Group>;
64256425
def mmovdir64b : Flag<["-"], "mmovdir64b">, Group<m_x86_Features_Group>;
64266426
def mno_movdir64b : Flag<["-"], "mno-movdir64b">, Group<m_x86_Features_Group>;
6427+
def mmovrs : Flag<["-"], "mmovrs">, Group<m_x86_Features_Group>;
6428+
def mno_movrs : Flag<["-"], "mno-movrs">, Group<m_x86_Features_Group>;
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def mmwaitx : Flag<["-"], "mmwaitx">, Group<m_x86_Features_Group>;
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def mno_mwaitx : Flag<["-"], "mno-mwaitx">, Group<m_x86_Features_Group>;
64296431
def mpku : Flag<["-"], "mpku">, Group<m_x86_Features_Group>;

‎clang/lib/Basic/Targets/X86.cpp

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Original file line numberDiff line numberDiff line change
@@ -348,6 +348,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
348348
HasSM4 = true;
349349
} else if (Feature == "+movbe") {
350350
HasMOVBE = true;
351+
} else if (Feature == "+movrs") {
352+
HasMOVRS = true;
351353
} else if (Feature == "+sgx") {
352354
HasSGX = true;
353355
} else if (Feature == "+cx8") {
@@ -915,6 +917,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
915917
Builder.defineMacro("__MOVDIRI__");
916918
if (HasMOVDIR64B)
917919
Builder.defineMacro("__MOVDIR64B__");
920+
if (HasMOVRS)
921+
Builder.defineMacro("__MOVRS__");
918922
if (HasPCONFIG)
919923
Builder.defineMacro("__PCONFIG__");
920924
if (HasPTWRITE)
@@ -1116,6 +1120,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
11161120
.Case("lzcnt", true)
11171121
.Case("mmx", true)
11181122
.Case("movbe", true)
1123+
.Case("movrs", true)
11191124
.Case("movdiri", true)
11201125
.Case("movdir64b", true)
11211126
.Case("mwaitx", true)
@@ -1233,6 +1238,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
12331238
.Case("lzcnt", HasLZCNT)
12341239
.Case("mmx", HasMMX)
12351240
.Case("movbe", HasMOVBE)
1241+
.Case("movrs", HasMOVRS)
12361242
.Case("movdiri", HasMOVDIRI)
12371243
.Case("movdir64b", HasMOVDIR64B)
12381244
.Case("mwaitx", HasMWAITX)

‎clang/lib/Basic/Targets/X86.h

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Original file line numberDiff line numberDiff line change
@@ -130,6 +130,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
130130
bool HasCLFLUSHOPT = false;
131131
bool HasCLWB = false;
132132
bool HasMOVBE = false;
133+
bool HasMOVRS = false;
133134
bool HasPREFETCHI = false;
134135
bool HasRDPID = false;
135136
bool HasRDPRU = false;

‎clang/lib/Headers/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -221,6 +221,8 @@ set(x86_files
221221
mm3dnow.h
222222
mmintrin.h
223223
movdirintrin.h
224+
movrs_avx10_2_512intrin.h
225+
movrs_avx10_2intrin.h
224226
mwaitxintrin.h
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nmmintrin.h
226228
pconfigintrin.h

‎clang/lib/Headers/immintrin.h

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Original file line numberDiff line numberDiff line change
@@ -605,6 +605,16 @@ _storebe_i64(void * __P, long long __D) {
605605
#include <movdirintrin.h>
606606
#endif
607607

608+
#if !defined(__SCE__) || __has_feature(modules) || \
609+
(defined(__AVX10_2__) && defined(__MOVRS__))
610+
#include <movrs_avx10_2intrin.h>
611+
#endif
612+
613+
#if !defined(__SCE__) || __has_feature(modules) || \
614+
(defined(__AVX10_2_512__) && defined(__MOVRS__))
615+
#include <movrs_avx10_2_512intrin.h>
616+
#endif
617+
608618
#if !defined(__SCE__) || __has_feature(modules) || defined(__PCONFIG__)
609619
#include <pconfigintrin.h>
610620
#endif

‎clang/lib/Headers/movrs_avx10_2_512intrin.h

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@@ -0,0 +1,98 @@
1+
/*===----- movrs_avx10_2_512intrin.h - AVX10.2-512-MOVRS intrinsics --------===
2+
*
3+
* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
* See https://llvm.org/LICENSE.txt for license information.
5+
* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
*
7+
*===-----------------------------------------------------------------------===
8+
*/
9+
#ifndef __IMMINTRIN_H
10+
#error \
11+
"Never use <movrs_avx10_2_512intrin.h> directly; include <immintrin.h> instead."
12+
#endif
13+
14+
#ifndef __MOVRS_AVX10_2_512INTRIN_H
15+
#define __MOVRS_AVX10_2_512INTRIN_H
16+
#ifdef __x86_64__
17+
18+
/* Define the default attributes for the functions in this file. */
19+
#define __DEFAULT_FN_ATTRS512 \
20+
__attribute__((__always_inline__, __nodebug__, \
21+
__target__("movrs, avx10.2-512"), __min_vector_width__(512)))
22+
23+
static __inline__ __m512i __DEFAULT_FN_ATTRS512
24+
_mm512_loadrs_epi8(void const *__A) {
25+
return (__m512i)__builtin_ia32_vmovrsb512((const __v64qi *)(__A));
26+
}
27+
28+
static __inline__ __m512i __DEFAULT_FN_ATTRS512
29+
_mm512_mask_loadrs_epi8(__m512i __W, __mmask64 __U, void const *__A) {
30+
return (__m512i)__builtin_ia32_selectb_512(
31+
(__mmask64)__U, (__v64qi)_mm512_loadrs_epi8(__A), (__v64qi)__W);
32+
}
33+
34+
static __inline__ __m512i __DEFAULT_FN_ATTRS512
35+
_mm512_maskz_loadrs_epi8(__mmask64 __U, void const *__A) {
36+
return (__m512i)__builtin_ia32_selectb_512((__mmask64)__U,
37+
(__v64qi)_mm512_loadrs_epi8(__A),
38+
(__v64qi)_mm512_setzero_si512());
39+
}
40+
41+
static __inline__ __m512i __DEFAULT_FN_ATTRS512
42+
_mm512_loadrs_epi32(void const *__A) {
43+
return (__m512i)__builtin_ia32_vmovrsd512((const __v16si *)(__A));
44+
}
45+
46+
static __inline__ __m512i __DEFAULT_FN_ATTRS512
47+
_mm512_mask_loadrs_epi32(__m512i __W, __mmask16 __U, void const *__A) {
48+
return (__m512i)__builtin_ia32_selectd_512(
49+
(__mmask16)__U, (__v16si)_mm512_loadrs_epi32(__A), (__v16si)__W);
50+
}
51+
52+
static __inline__ __m512i __DEFAULT_FN_ATTRS512
53+
_mm512_maskz_loadrs_epi32(__mmask16 __U, void const *__A) {
54+
return (__m512i)__builtin_ia32_selectd_512((__mmask16)__U,
55+
(__v16si)_mm512_loadrs_epi32(__A),
56+
(__v16si)_mm512_setzero_si512());
57+
}
58+
59+
static __inline__ __m512i __DEFAULT_FN_ATTRS512
60+
_mm512_loadrs_epi64(void const *__A) {
61+
return (__m512i)__builtin_ia32_vmovrsq512((const __v8di *)(__A));
62+
}
63+
64+
static __inline__ __m512i __DEFAULT_FN_ATTRS512
65+
_mm512_mask_loadrs_epi64(__m512i __W, __mmask8 __U, void const *__A) {
66+
return (__m512i)__builtin_ia32_selectq_512(
67+
(__mmask8)__U, (__v8di)_mm512_loadrs_epi64(__A), (__v8di)__W);
68+
}
69+
70+
static __inline__ __m512i __DEFAULT_FN_ATTRS512
71+
_mm512_maskz_loadrs_epi64(__mmask8 __U, void const *__A) {
72+
return (__m512i)__builtin_ia32_selectq_512((__mmask8)__U,
73+
(__v8di)_mm512_loadrs_epi64(__A),
74+
(__v8di)_mm512_setzero_si512());
75+
}
76+
77+
static __inline__ __m512i __DEFAULT_FN_ATTRS512
78+
_mm512_loadrs_epi16(void const *__A) {
79+
return (__m512i)__builtin_ia32_vmovrsw512((const __v32hi *)(__A));
80+
}
81+
82+
static __inline__ __m512i __DEFAULT_FN_ATTRS512
83+
_mm512_mask_loadrs_epi16(__m512i __W, __mmask32 __U, void const *__A) {
84+
return (__m512i)__builtin_ia32_selectw_512(
85+
(__mmask32)__U, (__v32hi)_mm512_loadrs_epi16(__A), (__v32hi)__W);
86+
}
87+
88+
static __inline__ __m512i __DEFAULT_FN_ATTRS512
89+
_mm512_maskz_loadrs_epi16(__mmask32 __U, void const *__A) {
90+
return (__m512i)__builtin_ia32_selectw_512((__mmask32)__U,
91+
(__v32hi)_mm512_loadrs_epi16(__A),
92+
(__v32hi)_mm512_setzero_si512());
93+
}
94+
95+
#undef __DEFAULT_FN_ATTRS512
96+
97+
#endif /* __x86_64__ */
98+
#endif /* __MOVRS_AVX10_2_512INTRIN_H */

‎clang/lib/Headers/movrs_avx10_2intrin.h

Lines changed: 174 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,174 @@
1+
/*===--------- movrs_avx10_2intrin.h - AVX10.2-MOVRS intrinsics ------------===
2+
*
3+
* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
* See https://llvm.org/LICENSE.txt for license information.
5+
* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
*
7+
*===-----------------------------------------------------------------------===
8+
*/
9+
#ifndef __IMMINTRIN_H
10+
#error \
11+
"Never use <movrs_avx10_2intrin.h> directly; include <immintrin.h> instead."
12+
#endif
13+
14+
#ifndef __MOVRS_AVX10_2INTRIN_H
15+
#define __MOVRS_AVX10_2INTRIN_H
16+
#ifdef __x86_64__
17+
18+
/* Define the default attributes for the functions in this file. */
19+
#define __DEFAULT_FN_ATTRS128 \
20+
__attribute__((__always_inline__, __nodebug__, \
21+
__target__("movrs,avx10.2-256"), __min_vector_width__(128)))
22+
#define __DEFAULT_FN_ATTRS256 \
23+
__attribute__((__always_inline__, __nodebug__, \
24+
__target__("movrs,avx10.2-256"), __min_vector_width__(256)))
25+
26+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
27+
_mm_loadrs_epi8(void const *__A) {
28+
return (__m128i)__builtin_ia32_vmovrsb128((const __v16qi *)(__A));
29+
}
30+
31+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
32+
_mm_mask_loadrs_epi8(__m128i __W, __mmask16 __U, void const *__A) {
33+
return (__m128i)__builtin_ia32_selectb_128(
34+
(__mmask16)__U, (__v16qi)_mm_loadrs_epi8(__A), (__v16qi)__W);
35+
}
36+
37+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
38+
_mm_maskz_loadrs_epi8(__mmask16 __U, void const *__A) {
39+
return (__m128i)__builtin_ia32_selectb_128((__mmask16)__U,
40+
(__v16qi)_mm_loadrs_epi8(__A),
41+
(__v16qi)_mm_setzero_si128());
42+
}
43+
44+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
45+
_mm256_loadrs_epi8(void const *__A) {
46+
return (__m256i)__builtin_ia32_vmovrsb256((const __v32qi *)(__A));
47+
}
48+
49+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
50+
_mm256_mask_loadrs_epi8(__m256i __W, __mmask32 __U, void const *__A) {
51+
return (__m256i)__builtin_ia32_selectb_256(
52+
(__mmask32)__U, (__v32qi)_mm256_loadrs_epi8(__A), (__v32qi)__W);
53+
}
54+
55+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
56+
_mm256_maskz_loadrs_epi8(__mmask32 __U, void const *__A) {
57+
return (__m256i)__builtin_ia32_selectb_256((__mmask32)__U,
58+
(__v32qi)_mm256_loadrs_epi8(__A),
59+
(__v32qi)_mm256_setzero_si256());
60+
}
61+
62+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
63+
_mm_loadrs_epi32(void const *__A) {
64+
return (__m128i)__builtin_ia32_vmovrsd128((const __v4si *)(__A));
65+
}
66+
67+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
68+
_mm_mask_loadrs_epi32(__m128i __W, __mmask8 __U, void const *__A) {
69+
return (__m128i)__builtin_ia32_selectd_128(
70+
(__mmask8)__U, (__v4si)_mm_loadrs_epi32(__A), (__v4si)__W);
71+
}
72+
73+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
74+
_mm_maskz_loadrs_epi32(__mmask8 __U, void const *__A) {
75+
return (__m128i)__builtin_ia32_selectd_128((__mmask8)__U,
76+
(__v4si)_mm_loadrs_epi32(__A),
77+
(__v4si)_mm_setzero_si128());
78+
}
79+
80+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
81+
_mm256_loadrs_epi32(void const *__A) {
82+
return (__m256i)__builtin_ia32_vmovrsd256((const __v8si *)(__A));
83+
}
84+
85+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
86+
_mm256_mask_loadrs_epi32(__m256i __W, __mmask8 __U, void const *__A) {
87+
return (__m256i)__builtin_ia32_selectd_256(
88+
(__mmask8)__U, (__v8si)_mm256_loadrs_epi32(__A), (__v8si)__W);
89+
}
90+
91+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
92+
_mm256_maskz_loadrs_epi32(__mmask8 __U, void const *__A) {
93+
return (__m256i)__builtin_ia32_selectd_256((__mmask8)__U,
94+
(__v8si)_mm256_loadrs_epi32(__A),
95+
(__v8si)_mm256_setzero_si256());
96+
}
97+
98+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
99+
_mm_loadrs_epi64(void const *__A) {
100+
return (__m128i)__builtin_ia32_vmovrsq128((const __v2di *)(__A));
101+
}
102+
103+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
104+
_mm_mask_loadrs_epi64(__m128i __W, __mmask8 __U, void const *__A) {
105+
return (__m128i)__builtin_ia32_selectq_128(
106+
(__mmask8)__U, (__v2di)_mm_loadrs_epi64(__A), (__v2di)__W);
107+
}
108+
109+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
110+
_mm_maskz_loadrs_epi64(__mmask8 __U, void const *__A) {
111+
return (__m128i)__builtin_ia32_selectq_128((__mmask8)__U,
112+
(__v2di)_mm_loadrs_epi64(__A),
113+
(__v2di)_mm_setzero_si128());
114+
}
115+
116+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
117+
_mm256_loadrs_epi64(void const *__A) {
118+
return (__m256i)__builtin_ia32_vmovrsq256((const __v4di *)(__A));
119+
}
120+
121+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
122+
_mm256_mask_loadrs_epi64(__m256i __W, __mmask8 __U, void const *__A) {
123+
return (__m256i)__builtin_ia32_selectq_256(
124+
(__mmask8)__U, (__v4di)_mm256_loadrs_epi64(__A), (__v4di)__W);
125+
}
126+
127+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
128+
_mm256_maskz_loadrs_epi64(__mmask8 __U, void const *__A) {
129+
return (__m256i)__builtin_ia32_selectq_256((__mmask8)__U,
130+
(__v4di)_mm256_loadrs_epi64(__A),
131+
(__v4di)_mm256_setzero_si256());
132+
}
133+
134+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
135+
_mm_loadrs_epi16(void const *__A) {
136+
return (__m128i)__builtin_ia32_vmovrsw128((const __v8hi *)(__A));
137+
}
138+
139+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
140+
_mm_mask_loadrs_epi16(__m128i __W, __mmask8 __U, void const *__A) {
141+
return (__m128i)__builtin_ia32_selectw_128(
142+
(__mmask8)__U, (__v8hi)_mm_loadrs_epi16(__A), (__v8hi)__W);
143+
}
144+
145+
static __inline__ __m128i __DEFAULT_FN_ATTRS128
146+
_mm_maskz_loadrs_epi16(__mmask8 __U, void const *__A) {
147+
return (__m128i)__builtin_ia32_selectw_128((__mmask8)__U,
148+
(__v8hi)_mm_loadrs_epi16(__A),
149+
(__v8hi)_mm_setzero_si128());
150+
}
151+
152+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
153+
_mm256_loadrs_epi16(void const *__A) {
154+
return (__m256i)__builtin_ia32_vmovrsw256((const __v16hi *)(__A));
155+
}
156+
157+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
158+
_mm256_mask_loadrs_epi16(__m256i __W, __mmask16 __U, void const *__A) {
159+
return (__m256i)__builtin_ia32_selectw_256(
160+
(__mmask16)__U, (__v16hi)_mm256_loadrs_epi16(__A), (__v16hi)__W);
161+
}
162+
163+
static __inline__ __m256i __DEFAULT_FN_ATTRS256
164+
_mm256_maskz_loadrs_epi16(__mmask16 __U, void const *__A) {
165+
return (__m256i)__builtin_ia32_selectw_256((__mmask16)__U,
166+
(__v16hi)_mm256_loadrs_epi16(__A),
167+
(__v16hi)_mm256_setzero_si256());
168+
}
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#undef __DEFAULT_FN_ATTRS128
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#undef __DEFAULT_FN_ATTRS256
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#endif /* __x86_64__ */
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#endif /* __MOVRS_AVX10_2INTRIN_H */

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