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[ELF] Pass Ctx & to TargetInfo. NFC
1 parent 75ad8b2 commit c3e4998

19 files changed

+132
-132
lines changed

‎lld/ELF/Arch/AArch64.cpp

+7-7
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ uint64_t elf::getAArch64Page(uint64_t expr) {
3131
namespace {
3232
class AArch64 : public TargetInfo {
3333
public:
34-
AArch64();
34+
AArch64(Ctx &);
3535
RelExpr getRelExpr(RelType type, const Symbol &s,
3636
const uint8_t *loc) const override;
3737
RelType getDynRel(RelType type) const override;
@@ -76,7 +76,7 @@ static uint64_t getBits(uint64_t val, int start, int end) {
7676
return (val >> start) & mask;
7777
}
7878

79-
AArch64::AArch64() {
79+
AArch64::AArch64(Ctx &ctx) : TargetInfo(ctx) {
8080
copyRel = R_AARCH64_COPY;
8181
relativeRel = R_AARCH64_RELATIVE;
8282
iRelativeRel = R_AARCH64_IRELATIVE;
@@ -960,7 +960,7 @@ void AArch64::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
960960
namespace {
961961
class AArch64BtiPac final : public AArch64 {
962962
public:
963-
AArch64BtiPac();
963+
AArch64BtiPac(Ctx &);
964964
void writePltHeader(uint8_t *buf) const override;
965965
void writePlt(uint8_t *buf, const Symbol &sym,
966966
uint64_t pltEntryAddr) const override;
@@ -971,7 +971,7 @@ class AArch64BtiPac final : public AArch64 {
971971
};
972972
} // namespace
973973

974-
AArch64BtiPac::AArch64BtiPac() {
974+
AArch64BtiPac::AArch64BtiPac(Ctx &ctx) : AArch64(ctx) {
975975
btiHeader = (ctx.arg.andFeatures & GNU_PROPERTY_AARCH64_FEATURE_1_BTI);
976976
// A BTI (Branch Target Indicator) Plt Entry is only required if the
977977
// address of the PLT entry can be taken by the program, which permits an
@@ -1176,12 +1176,12 @@ void lld::elf::createTaggedSymbols(const SmallVector<ELFFileBase *, 0> &files) {
11761176
}
11771177
}
11781178

1179-
TargetInfo *elf::getAArch64TargetInfo() {
1179+
TargetInfo *elf::getAArch64TargetInfo(Ctx &ctx) {
11801180
if ((ctx.arg.andFeatures & GNU_PROPERTY_AARCH64_FEATURE_1_BTI) ||
11811181
ctx.arg.zPacPlt) {
1182-
static AArch64BtiPac t;
1182+
static AArch64BtiPac t(ctx);
11831183
return &t;
11841184
}
1185-
static AArch64 t;
1185+
static AArch64 t(ctx);
11861186
return &t;
11871187
}

‎lld/ELF/Arch/AMDGPU.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ class AMDGPU final : public TargetInfo {
2828
uint32_t calcEFlagsV6() const;
2929

3030
public:
31-
AMDGPU();
31+
AMDGPU(Ctx &);
3232
uint32_t calcEFlags() const override;
3333
void relocate(uint8_t *loc, const Relocation &rel,
3434
uint64_t val) const override;
@@ -39,7 +39,7 @@ class AMDGPU final : public TargetInfo {
3939
};
4040
} // namespace
4141

42-
AMDGPU::AMDGPU() {
42+
AMDGPU::AMDGPU(Ctx &ctx) : TargetInfo(ctx) {
4343
relativeRel = R_AMDGPU_RELATIVE64;
4444
gotRel = R_AMDGPU_ABS64;
4545
symbolicRel = R_AMDGPU_ABS64;
@@ -219,7 +219,7 @@ int64_t AMDGPU::getImplicitAddend(const uint8_t *buf, RelType type) const {
219219
}
220220
}
221221

222-
TargetInfo *elf::getAMDGPUTargetInfo() {
223-
static AMDGPU target;
222+
TargetInfo *elf::getAMDGPUTargetInfo(Ctx &ctx) {
223+
static AMDGPU target(ctx);
224224
return &target;
225225
}

‎lld/ELF/Arch/ARM.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ using namespace llvm::object;
2828
namespace {
2929
class ARM final : public TargetInfo {
3030
public:
31-
ARM();
31+
ARM(Ctx &);
3232
uint32_t calcEFlags() const override;
3333
RelExpr getRelExpr(RelType type, const Symbol &s,
3434
const uint8_t *loc) const override;
@@ -54,7 +54,7 @@ enum class CodeState { Data = 0, Thumb = 2, Arm = 4 };
5454

5555
static DenseMap<InputSection *, SmallVector<const Defined *, 0>> sectionMap{};
5656

57-
ARM::ARM() {
57+
ARM::ARM(Ctx &ctx) : TargetInfo(ctx) {
5858
copyRel = R_ARM_COPY;
5959
relativeRel = R_ARM_RELATIVE;
6060
iRelativeRel = R_ARM_IRELATIVE;
@@ -1533,8 +1533,8 @@ template <typename ELFT> void elf::writeARMCmseImportLib() {
15331533
"': " + toString(std::move(e)));
15341534
}
15351535

1536-
TargetInfo *elf::getARMTargetInfo() {
1537-
static ARM target;
1536+
TargetInfo *elf::getARMTargetInfo(Ctx &ctx) {
1537+
static ARM target(ctx);
15381538
return &target;
15391539
}
15401540

‎lld/ELF/Arch/AVR.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ using namespace lld::elf;
4343
namespace {
4444
class AVR final : public TargetInfo {
4545
public:
46-
AVR() { needsThunks = true; }
46+
AVR(Ctx &ctx) : TargetInfo(ctx) { needsThunks = true; }
4747
uint32_t calcEFlags() const override;
4848
RelExpr getRelExpr(RelType type, const Symbol &s,
4949
const uint8_t *loc) const override;
@@ -267,8 +267,8 @@ void AVR::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
267267
}
268268
}
269269

270-
TargetInfo *elf::getAVRTargetInfo() {
271-
static AVR target;
270+
TargetInfo *elf::getAVRTargetInfo(Ctx &ctx) {
271+
static AVR target(ctx);
272272
return &target;
273273
}
274274

‎lld/ELF/Arch/Hexagon.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ using namespace lld::elf;
2424
namespace {
2525
class Hexagon final : public TargetInfo {
2626
public:
27-
Hexagon();
27+
Hexagon(Ctx &);
2828
uint32_t calcEFlags() const override;
2929
RelExpr getRelExpr(RelType type, const Symbol &s,
3030
const uint8_t *loc) const override;
@@ -38,7 +38,7 @@ class Hexagon final : public TargetInfo {
3838
};
3939
} // namespace
4040

41-
Hexagon::Hexagon() {
41+
Hexagon::Hexagon(Ctx &ctx) : TargetInfo(ctx) {
4242
pltRel = R_HEX_JMP_SLOT;
4343
relativeRel = R_HEX_RELATIVE;
4444
gotRel = R_HEX_GLOB_DAT;
@@ -404,7 +404,7 @@ int64_t Hexagon::getImplicitAddend(const uint8_t *buf, RelType type) const {
404404
}
405405
}
406406

407-
TargetInfo *elf::getHexagonTargetInfo() {
408-
static Hexagon target;
407+
TargetInfo *elf::getHexagonTargetInfo(Ctx &ctx) {
408+
static Hexagon target(ctx);
409409
return &target;
410410
}

‎lld/ELF/Arch/LoongArch.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ using namespace lld::elf;
2424
namespace {
2525
class LoongArch final : public TargetInfo {
2626
public:
27-
LoongArch();
27+
LoongArch(Ctx &);
2828
uint32_t calcEFlags() const override;
2929
int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
3030
void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
@@ -170,7 +170,7 @@ static void handleUleb128(uint8_t *loc, uint64_t val) {
170170
encodeULEB128((orig + val) & mask, loc, count);
171171
}
172172

173-
LoongArch::LoongArch() {
173+
LoongArch::LoongArch(Ctx &ctx) : TargetInfo(ctx) {
174174
// The LoongArch ISA itself does not have a limit on page sizes. According to
175175
// the ISA manual, the PS (page size) field in MTLB entries and CSR.STLBPS is
176176
// 6 bits wide, meaning the maximum page size is 2^63 which is equivalent to
@@ -893,7 +893,7 @@ void LoongArch::finalizeRelax(int passes) const {
893893
}
894894
}
895895

896-
TargetInfo *elf::getLoongArchTargetInfo() {
897-
static LoongArch target;
896+
TargetInfo *elf::getLoongArchTargetInfo(Ctx &ctx) {
897+
static LoongArch target(ctx);
898898
return &target;
899899
}

‎lld/ELF/Arch/MSP430.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -31,15 +31,15 @@ using namespace lld::elf;
3131
namespace {
3232
class MSP430 final : public TargetInfo {
3333
public:
34-
MSP430();
34+
MSP430(Ctx &);
3535
RelExpr getRelExpr(RelType type, const Symbol &s,
3636
const uint8_t *loc) const override;
3737
void relocate(uint8_t *loc, const Relocation &rel,
3838
uint64_t val) const override;
3939
};
4040
} // namespace
4141

42-
MSP430::MSP430() {
42+
MSP430::MSP430(Ctx &ctx) : TargetInfo(ctx) {
4343
// mov.b #0, r3
4444
trapInstr = {0x43, 0x43, 0x43, 0x43};
4545
}
@@ -88,7 +88,7 @@ void MSP430::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
8888
}
8989
}
9090

91-
TargetInfo *elf::getMSP430TargetInfo() {
92-
static MSP430 target;
91+
TargetInfo *elf::getMSP430TargetInfo(Ctx &ctx) {
92+
static MSP430 target(ctx);
9393
return &target;
9494
}

‎lld/ELF/Arch/Mips.cpp

+23-10
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ using namespace lld::elf;
2323
namespace {
2424
template <class ELFT> class MIPS final : public TargetInfo {
2525
public:
26-
MIPS();
26+
MIPS(Ctx &);
2727
uint32_t calcEFlags() const override;
2828
RelExpr getRelExpr(RelType type, const Symbol &s,
2929
const uint8_t *loc) const override;
@@ -42,7 +42,7 @@ template <class ELFT> class MIPS final : public TargetInfo {
4242
};
4343
} // namespace
4444

45-
template <class ELFT> MIPS<ELFT>::MIPS() {
45+
template <class ELFT> MIPS<ELFT>::MIPS(Ctx &ctx) : TargetInfo(ctx) {
4646
gotPltHeaderEntriesNum = 2;
4747
defaultMaxPageSize = 65536;
4848
pltEntrySize = 16;
@@ -778,16 +778,29 @@ template <class ELFT> bool elf::isMipsPIC(const Defined *sym) {
778778
return cast<ObjFile<ELFT>>(file)->getObj().getHeader().e_flags & EF_MIPS_PIC;
779779
}
780780

781-
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
782-
static MIPS<ELFT> target;
783-
return &target;
781+
TargetInfo *elf::getMipsTargetInfo(Ctx &ctx) {
782+
switch (ctx.arg.ekind) {
783+
case ELF32LEKind: {
784+
static MIPS<ELF32LE> t(ctx);
785+
return &t;
786+
}
787+
case ELF32BEKind: {
788+
static MIPS<ELF32BE> t(ctx);
789+
return &t;
790+
}
791+
case ELF64LEKind: {
792+
static MIPS<ELF64LE> t(ctx);
793+
return &t;
794+
}
795+
case ELF64BEKind: {
796+
static MIPS<ELF64BE> t(ctx);
797+
return &t;
798+
}
799+
default:
800+
llvm_unreachable("unsupported target");
801+
}
784802
}
785803

786-
template TargetInfo *elf::getMipsTargetInfo<ELF32LE>();
787-
template TargetInfo *elf::getMipsTargetInfo<ELF32BE>();
788-
template TargetInfo *elf::getMipsTargetInfo<ELF64LE>();
789-
template TargetInfo *elf::getMipsTargetInfo<ELF64BE>();
790-
791804
template bool elf::isMipsPIC<ELF32LE>(const Defined *);
792805
template bool elf::isMipsPIC<ELF32BE>(const Defined *);
793806
template bool elf::isMipsPIC<ELF64LE>(const Defined *);

‎lld/ELF/Arch/PPC.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ using namespace lld::elf;
2626
namespace {
2727
class PPC final : public TargetInfo {
2828
public:
29-
PPC();
29+
PPC(Ctx &);
3030
RelExpr getRelExpr(RelType type, const Symbol &s,
3131
const uint8_t *loc) const override;
3232
RelType getDynRel(RelType type) const override;
@@ -152,7 +152,7 @@ void elf::writePPC32GlinkSection(uint8_t *buf, size_t numEntries) {
152152
write32(buf, 0x60000000);
153153
}
154154

155-
PPC::PPC() {
155+
PPC::PPC(Ctx &ctx) : TargetInfo(ctx) {
156156
copyRel = R_PPC_COPY;
157157
gotRel = R_PPC_GLOB_DAT;
158158
pltRel = R_PPC_JMP_SLOT;
@@ -525,7 +525,7 @@ void PPC::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
525525
}
526526
}
527527

528-
TargetInfo *elf::getPPCTargetInfo() {
529-
static PPC target;
528+
TargetInfo *elf::getPPCTargetInfo(Ctx &ctx) {
529+
static PPC target(ctx);
530530
return &target;
531531
}

‎lld/ELF/Arch/PPC64.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -168,7 +168,7 @@ enum class LegacyToPrefixMask : uint64_t {
168168

169169
class PPC64 final : public TargetInfo {
170170
public:
171-
PPC64();
171+
PPC64(Ctx &);
172172
int getTlsGdRelaxSkip(RelType type) const override;
173173
uint32_t calcEFlags() const override;
174174
RelExpr getRelExpr(RelType type, const Symbol &s,
@@ -578,7 +578,7 @@ static uint64_t readPrefixedInstruction(const uint8_t *loc) {
578578
return ctx.arg.isLE ? (fullInstr << 32 | fullInstr >> 32) : fullInstr;
579579
}
580580

581-
PPC64::PPC64() {
581+
PPC64::PPC64(Ctx &ctx) : TargetInfo(ctx) {
582582
copyRel = R_PPC64_COPY;
583583
gotRel = R_PPC64_GLOB_DAT;
584584
pltRel = R_PPC64_JMP_SLOT;
@@ -1750,7 +1750,7 @@ bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end,
17501750
return true;
17511751
}
17521752

1753-
TargetInfo *elf::getPPC64TargetInfo() {
1754-
static PPC64 target;
1753+
TargetInfo *elf::getPPC64TargetInfo(Ctx &ctx) {
1754+
static PPC64 target(ctx);
17551755
return &target;
17561756
}

‎lld/ELF/Arch/RISCV.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ namespace {
2929

3030
class RISCV final : public TargetInfo {
3131
public:
32-
RISCV();
32+
RISCV(Ctx &);
3333
uint32_t calcEFlags() const override;
3434
int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
3535
void writeGotHeader(uint8_t *buf) const override;
@@ -107,7 +107,7 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
107107
(extractBits(imm, 4, 0) << 7);
108108
}
109109

110-
RISCV::RISCV() {
110+
RISCV::RISCV(Ctx &ctx) : TargetInfo(ctx) {
111111
copyRel = R_RISCV_COPY;
112112
pltRel = R_RISCV_JUMP_SLOT;
113113
relativeRel = R_RISCV_RELATIVE;
@@ -1328,7 +1328,7 @@ void elf::mergeRISCVAttributesSections() {
13281328
mergeAttributesSection(sections));
13291329
}
13301330

1331-
TargetInfo *elf::getRISCVTargetInfo() {
1332-
static RISCV target;
1331+
TargetInfo *elf::getRISCVTargetInfo(Ctx &ctx) {
1332+
static RISCV target(ctx);
13331333
return &target;
13341334
}

‎lld/ELF/Arch/SPARCV9.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ using namespace lld::elf;
2121
namespace {
2222
class SPARCV9 final : public TargetInfo {
2323
public:
24-
SPARCV9();
24+
SPARCV9(Ctx &);
2525
RelExpr getRelExpr(RelType type, const Symbol &s,
2626
const uint8_t *loc) const override;
2727
void writePlt(uint8_t *buf, const Symbol &sym,
@@ -31,7 +31,7 @@ class SPARCV9 final : public TargetInfo {
3131
};
3232
} // namespace
3333

34-
SPARCV9::SPARCV9() {
34+
SPARCV9::SPARCV9(Ctx &ctx) : TargetInfo(ctx) {
3535
copyRel = R_SPARC_COPY;
3636
gotRel = R_SPARC_GLOB_DAT;
3737
pltRel = R_SPARC_JMP_SLOT;
@@ -193,7 +193,7 @@ void SPARCV9::writePlt(uint8_t *buf, const Symbol & /*sym*/,
193193
relocateNoSym(buf + 4, R_SPARC_WDISP19, -(off + 4 - pltEntrySize));
194194
}
195195

196-
TargetInfo *elf::getSPARCV9TargetInfo() {
197-
static SPARCV9 target;
196+
TargetInfo *elf::getSPARCV9TargetInfo(Ctx &ctx) {
197+
static SPARCV9 target(ctx);
198198
return &target;
199199
}

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