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[AArch64] Enable FeatureFuseAdrpAdd for all Arm cpus
The commit D120104 enabled FeatureFuseAdrpAdd for -mcpu=generic, allowing the linker to relax adrp;add pairs where possible. D132075 extended that to neoverse-n1, this patch extends it to all other cortex and neoverse cpus for the same reasons. Differential Revision: https://reviews.llvm.org/D134521
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‎llvm/lib/Target/AArch64/AArch64.td

+18-2
Original file line numberDiff line numberDiff line change
@@ -668,19 +668,22 @@ def TuneA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
668668
def TuneA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
669669
"Cortex-A53 ARM processors", [
670670
FeatureFuseAES,
671+
FeatureFuseAdrpAdd,
671672
FeatureBalanceFPOps,
672673
FeatureCustomCheapAsMoveHandling,
673674
FeaturePostRAScheduler]>;
674675

675676
def TuneA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
676677
"Cortex-A55 ARM processors", [
677678
FeatureFuseAES,
679+
FeatureFuseAdrpAdd,
678680
FeaturePostRAScheduler,
679681
FeatureFuseAddress]>;
680682

681683
def TuneA510 : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510",
682684
"Cortex-A510 ARM processors", [
683685
FeatureFuseAES,
686+
FeatureFuseAdrpAdd,
684687
FeaturePostRAScheduler
685688
]>;
686689

@@ -709,27 +712,32 @@ def TuneA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
709712

710713
def TuneA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
711714
"Cortex-A73 ARM processors", [
712-
FeatureFuseAES]>;
715+
FeatureFuseAES,
716+
FeatureFuseAdrpAdd]>;
713717

714718
def TuneA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
715719
"Cortex-A75 ARM processors", [
716-
FeatureFuseAES]>;
720+
FeatureFuseAES,
721+
FeatureFuseAdrpAdd]>;
717722

718723
def TuneA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
719724
"Cortex-A76 ARM processors", [
720725
FeatureFuseAES,
726+
FeatureFuseAdrpAdd,
721727
FeatureLSLFast]>;
722728

723729
def TuneA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77",
724730
"Cortex-A77 ARM processors", [
725731
FeatureCmpBccFusion,
726732
FeatureFuseAES,
733+
FeatureFuseAdrpAdd,
727734
FeatureLSLFast]>;
728735

729736
def TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78",
730737
"Cortex-A78 ARM processors", [
731738
FeatureCmpBccFusion,
732739
FeatureFuseAES,
740+
FeatureFuseAdrpAdd,
733741
FeatureLSLFast,
734742
FeaturePostRAScheduler]>;
735743

@@ -738,13 +746,15 @@ def TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily",
738746
"Cortex-A78C ARM processors", [
739747
FeatureCmpBccFusion,
740748
FeatureFuseAES,
749+
FeatureFuseAdrpAdd,
741750
FeatureLSLFast,
742751
FeaturePostRAScheduler]>;
743752

744753
def TuneA710 : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710",
745754
"Cortex-A710 ARM processors", [
746755
FeatureCmpBccFusion,
747756
FeatureFuseAES,
757+
FeatureFuseAdrpAdd,
748758
FeatureLSLFast,
749759
FeaturePostRAScheduler]>;
750760

@@ -757,13 +767,15 @@ def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
757767
"Cortex-X1 ARM processors", [
758768
FeatureCmpBccFusion,
759769
FeatureFuseAES,
770+
FeatureFuseAdrpAdd,
760771
FeatureLSLFast,
761772
FeaturePostRAScheduler]>;
762773

763774
def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2",
764775
"Cortex-X2 ARM processors", [
765776
FeatureCmpBccFusion,
766777
FeatureFuseAES,
778+
FeatureFuseAdrpAdd,
767779
FeatureLSLFast,
768780
FeaturePostRAScheduler]>;
769781

@@ -941,6 +953,7 @@ def TuneFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
941953
def TuneNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", "NeoverseE1",
942954
"Neoverse E1 ARM processors", [
943955
FeatureFuseAES,
956+
FeatureFuseAdrpAdd,
944957
FeaturePostRAScheduler]>;
945958

946959
def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1",
@@ -953,18 +966,21 @@ def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1
953966
def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2",
954967
"Neoverse N2 ARM processors", [
955968
FeatureFuseAES,
969+
FeatureFuseAdrpAdd,
956970
FeatureLSLFast,
957971
FeaturePostRAScheduler]>;
958972

959973
def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB",
960974
"Neoverse 512-TVB ARM processors", [
961975
FeatureFuseAES,
976+
FeatureFuseAdrpAdd,
962977
FeatureLSLFast,
963978
FeaturePostRAScheduler]>;
964979

965980
def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1",
966981
"Neoverse V1 ARM processors", [
967982
FeatureFuseAES,
983+
FeatureFuseAdrpAdd,
968984
FeatureLSLFast,
969985
FeaturePostRAScheduler]>;
970986

‎llvm/test/CodeGen/AArch64/misched-fusion-addadrp.ll

+37
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-adrp-add | FileCheck %s
2+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=generic | FileCheck %s
3+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 | FileCheck %s
4+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a55 | FileCheck %s
5+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a510 | FileCheck %s
6+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s
7+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a75 | FileCheck %s
8+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a76 | FileCheck %s
9+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a77 | FileCheck %s
10+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a78 | FileCheck %s
11+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a710 | FileCheck %s
12+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n1 | FileCheck %s
13+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-v1 | FileCheck %s
14+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n2 | FileCheck %s
15+
16+
@g = common local_unnamed_addr global i8* null, align 8
17+
18+
define dso_local i8* @addldr(i32 %a, i32 %b) {
19+
; CHECK-LABEL: addldr:
20+
; CHECK: adrp [[R:x[0-9]+]], addldr
21+
; CHECK-NEXT: add {{x[0-9]+}}, [[R]], :lo12:addldr
22+
entry:
23+
%add = add nsw i32 %b, %a
24+
%idx.ext = sext i32 %add to i64
25+
%add.ptr = getelementptr i8, i8* bitcast (i8* (i32, i32)* @addldr to i8*), i64 %idx.ext
26+
store i8* %add.ptr, i8** @g, align 8
27+
ret i8* %add.ptr
28+
}
29+
30+
31+
define double @litf() {
32+
; CHECK-LABEL: litf:
33+
; CHECK: adrp [[ADDR:x[0-9]+]], [[CSTLABEL:.LCP.*]]
34+
; CHECK-NEXT: ldr {{d[0-9]+}}, {{[[]}}[[ADDR]], :lo12:[[CSTLABEL]]{{[]]}}
35+
entry:
36+
ret double 0x400921FB54442D18
37+
}

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