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Cleanup x86_mmx after removing IR type (#100646)
After #98505, the textual IR keyword `x86_mmx` was temporarily made to parse as `<1 x i64>`, so as not to require a lot of test update noise. This completes the removal of the type, by removing the`x86_mmx` keyword from the IR parser, and making the (now no-op) test updates via `sed -i 's/\bx86_mmx\b/<1 x i64>/g' $(git grep -l x86_mmx llvm/test/)`. Resulting bitcasts from <1 x i64> to itself were then manually deleted. Changes to llvm/test/Bitcode/compatibility-$VERSION.ll were reverted, as they're intended to be equivalent to the .bc file, if parsed by old LLVM, so shouldn't be updated. A few tests were removed, as they're no longer testing anything, in the following files: - llvm/test/Transforms/GlobalOpt/x86_mmx_load.ll - llvm/test/Transforms/InstCombine/cast.ll - llvm/test/Transforms/InstSimplify/ConstProp/gep-zeroinit-vector.ll Works towards issue #98272.
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‎llvm/lib/AsmParser/LLLexer.cpp

-2
Original file line numberDiff line numberDiff line change
@@ -838,8 +838,6 @@ lltok::Kind LLLexer::LexIdentifier() {
838838
TYPEKEYWORD("ppc_fp128", Type::getPPC_FP128Ty(Context));
839839
TYPEKEYWORD("label", Type::getLabelTy(Context));
840840
TYPEKEYWORD("metadata", Type::getMetadataTy(Context));
841-
TYPEKEYWORD("x86_mmx", llvm::FixedVectorType::get(
842-
llvm::IntegerType::get(Context, 64), 1));
843841
TYPEKEYWORD("x86_amx", Type::getX86_AMXTy(Context));
844842
TYPEKEYWORD("token", Type::getTokenTy(Context));
845843
TYPEKEYWORD("ptr", PointerType::getUnqual(Context));

‎llvm/test/Bindings/llvm-c/echo.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ define void @types() {
7070
%9 = alloca [3 x i22], align 4
7171
%10 = alloca ptr addrspace(5), align 8
7272
%11 = alloca <5 x ptr>, align 64
73-
%12 = alloca x86_mmx, align 8
73+
%12 = alloca <1 x i64>, align 8
7474
ret void
7575
}
7676

‎llvm/test/Bitcode/compatibility.ll

-2
Original file line numberDiff line numberDiff line change
@@ -1112,8 +1112,6 @@ define void @typesystem() {
11121112
; CHECK: %t5 = alloca x86_fp80
11131113
%t6 = alloca ppc_fp128
11141114
; CHECK: %t6 = alloca ppc_fp128
1115-
%t7 = alloca x86_mmx
1116-
; CHECK: %t7 = alloca <1 x i64>
11171115
%t8 = alloca ptr
11181116
; CHECK: %t8 = alloca ptr
11191117
%t9 = alloca <4 x i32>

‎llvm/test/CodeGen/X86/2007-05-15-maskmovq.ll

+2-4
Original file line numberDiff line numberDiff line change
@@ -25,10 +25,8 @@ define void @test(<1 x i64> %c64, <1 x i64> %mask1, ptr %P) {
2525
; CHECK-NEXT: popl %edi
2626
; CHECK-NEXT: retl
2727
entry:
28-
%tmp4 = bitcast <1 x i64> %mask1 to x86_mmx ; <x86_mmx> [#uses=1]
29-
%tmp6 = bitcast <1 x i64> %c64 to x86_mmx ; <x86_mmx> [#uses=1]
30-
tail call void @llvm.x86.mmx.maskmovq( x86_mmx %tmp4, x86_mmx %tmp6, ptr %P )
28+
tail call void @llvm.x86.mmx.maskmovq( <1 x i64> %mask1, <1 x i64> %c64, ptr %P )
3129
ret void
3230
}
3331

34-
declare void @llvm.x86.mmx.maskmovq(x86_mmx, x86_mmx, ptr)
32+
declare void @llvm.x86.mmx.maskmovq(<1 x i64>, <1 x i64>, ptr)

‎llvm/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll

+4-6
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | FileCheck %s
33

4-
@R = external global x86_mmx ; <ptr> [#uses=1]
4+
@R = external global <1 x i64> ; <ptr> [#uses=1]
55

66
define void @foo(<1 x i64> %A, <1 x i64> %B) nounwind {
77
; CHECK-LABEL: foo:
@@ -14,13 +14,11 @@ define void @foo(<1 x i64> %A, <1 x i64> %B) nounwind {
1414
; CHECK-NEXT: emms
1515
; CHECK-NEXT: retq
1616
entry:
17-
%tmp4 = bitcast <1 x i64> %B to x86_mmx ; <<4 x i16>> [#uses=1]
18-
%tmp6 = bitcast <1 x i64> %A to x86_mmx ; <<4 x i16>> [#uses=1]
19-
%tmp7 = tail call x86_mmx @llvm.x86.mmx.paddus.w( x86_mmx %tmp6, x86_mmx %tmp4 ) ; <x86_mmx> [#uses=1]
20-
store x86_mmx %tmp7, ptr @R
17+
%tmp7 = tail call <1 x i64> @llvm.x86.mmx.paddus.w( <1 x i64> %A, <1 x i64> %B ) ; <<1 x i64>> [#uses=1]
18+
store <1 x i64> %tmp7, ptr @R
2119
tail call void @llvm.x86.mmx.emms( )
2220
ret void
2321
}
2422

25-
declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx)
23+
declare <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64>, <1 x i64>)
2624
declare void @llvm.x86.mmx.emms()

‎llvm/test/CodeGen/X86/2008-04-08-CoalescerCrash.ll

+4-4
Original file line numberDiff line numberDiff line change
@@ -5,15 +5,15 @@ entry:
55
tail call void asm sideeffect "# top of block", "~{dirflag},~{fpsr},~{flags},~{di},~{si},~{dx},~{cx},~{ax}"( ) nounwind
66
tail call void asm sideeffect ".file \224443946.c\22", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
77
tail call void asm sideeffect ".line 8", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
8-
%tmp1 = tail call x86_mmx asm sideeffect "movd $1, $0", "=={mm4},{bp},~{dirflag},~{fpsr},~{flags},~{memory}"( i32 undef ) nounwind ; <x86_mmx> [#uses=1]
8+
%tmp1 = tail call <1 x i64> asm sideeffect "movd $1, $0", "=={mm4},{bp},~{dirflag},~{fpsr},~{flags},~{memory}"( i32 undef ) nounwind ; <<1 x i64>> [#uses=1]
99
tail call void asm sideeffect ".file \224443946.c\22", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
1010
tail call void asm sideeffect ".line 9", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
11-
%tmp3 = tail call i32 asm sideeffect "movd $1, $0", "=={bp},{mm3},~{dirflag},~{fpsr},~{flags},~{memory}"( x86_mmx undef ) nounwind ; <i32> [#uses=1]
11+
%tmp3 = tail call i32 asm sideeffect "movd $1, $0", "=={bp},{mm3},~{dirflag},~{fpsr},~{flags},~{memory}"( <1 x i64> undef ) nounwind ; <i32> [#uses=1]
1212
tail call void asm sideeffect ".file \224443946.c\22", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
1313
tail call void asm sideeffect ".line 10", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
14-
tail call void asm sideeffect "movntq $0, 0($1,$2)", "{mm0},{di},{bp},~{dirflag},~{fpsr},~{flags},~{memory}"( x86_mmx undef, i32 undef, i32 %tmp3 ) nounwind
14+
tail call void asm sideeffect "movntq $0, 0($1,$2)", "{mm0},{di},{bp},~{dirflag},~{fpsr},~{flags},~{memory}"( <1 x i64> undef, i32 undef, i32 %tmp3 ) nounwind
1515
tail call void asm sideeffect ".file \224443946.c\22", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
1616
tail call void asm sideeffect ".line 11", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
17-
%tmp8 = tail call i32 asm sideeffect "movd $1, $0", "=={bp},{mm4},~{dirflag},~{fpsr},~{flags},~{memory}"( x86_mmx %tmp1 ) nounwind ; <i32> [#uses=0]
17+
%tmp8 = tail call i32 asm sideeffect "movd $1, $0", "=={bp},{mm4},~{dirflag},~{fpsr},~{flags},~{memory}"( <1 x i64> %tmp1 ) nounwind ; <i32> [#uses=0]
1818
ret i32 undef
1919
}

‎llvm/test/CodeGen/X86/2008-08-23-64Bit-maskmovq.ll

+4-4
Original file line numberDiff line numberDiff line change
@@ -17,13 +17,13 @@ entry:
1717
br i1 false, label %bb.nph144.split, label %bb133
1818

1919
bb.nph144.split: ; preds = %entry
20-
%tmp = bitcast <8 x i8> zeroinitializer to x86_mmx
21-
%tmp2 = bitcast <8 x i8> zeroinitializer to x86_mmx
22-
tail call void @llvm.x86.mmx.maskmovq( x86_mmx %tmp, x86_mmx %tmp2, ptr null ) nounwind
20+
%tmp = bitcast <8 x i8> zeroinitializer to <1 x i64>
21+
%tmp2 = bitcast <8 x i8> zeroinitializer to <1 x i64>
22+
tail call void @llvm.x86.mmx.maskmovq( <1 x i64> %tmp, <1 x i64> %tmp2, ptr null ) nounwind
2323
unreachable
2424

2525
bb133: ; preds = %entry
2626
ret void
2727
}
2828

29-
declare void @llvm.x86.mmx.maskmovq(x86_mmx, x86_mmx, ptr) nounwind
29+
declare void @llvm.x86.mmx.maskmovq(<1 x i64>, <1 x i64>, ptr) nounwind

‎llvm/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll

+7-7
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ entry:
2626

2727
; This is how to get MMX instructions.
2828

29-
define <2 x double> @a2(x86_mmx %x) nounwind {
29+
define <2 x double> @a2(<1 x i64> %x) nounwind {
3030
; CHECK-LABEL: a2:
3131
; CHECK: # %bb.0: # %entry
3232
; CHECK-NEXT: pushl %ebp
@@ -42,11 +42,11 @@ define <2 x double> @a2(x86_mmx %x) nounwind {
4242
; CHECK-NEXT: popl %ebp
4343
; CHECK-NEXT: retl
4444
entry:
45-
%y = tail call <2 x double> @llvm.x86.sse.cvtpi2pd(x86_mmx %x)
45+
%y = tail call <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64> %x)
4646
ret <2 x double> %y
4747
}
4848

49-
define x86_mmx @b2(<2 x double> %x) nounwind {
49+
define <1 x i64> @b2(<2 x double> %x) nounwind {
5050
; CHECK-LABEL: b2:
5151
; CHECK: # %bb.0: # %entry
5252
; CHECK-NEXT: pushl %ebp
@@ -61,9 +61,9 @@ define x86_mmx @b2(<2 x double> %x) nounwind {
6161
; CHECK-NEXT: popl %ebp
6262
; CHECK-NEXT: retl
6363
entry:
64-
%y = tail call x86_mmx @llvm.x86.sse.cvttpd2pi (<2 x double> %x)
65-
ret x86_mmx %y
64+
%y = tail call <1 x i64> @llvm.x86.sse.cvttpd2pi (<2 x double> %x)
65+
ret <1 x i64> %y
6666
}
6767

68-
declare <2 x double> @llvm.x86.sse.cvtpi2pd(x86_mmx)
69-
declare x86_mmx @llvm.x86.sse.cvttpd2pi(<2 x double>)
68+
declare <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64>)
69+
declare <1 x i64> @llvm.x86.sse.cvttpd2pi(<2 x double>)

‎llvm/test/CodeGen/X86/2011-06-14-mmx-inlineasm.ll

+4-4
Original file line numberDiff line numberDiff line change
@@ -3,22 +3,22 @@
33
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
44
target triple = "i386-apple-macosx10.6.6"
55

6-
%0 = type { x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx }
6+
%0 = type { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> }
77

88
define i32 @pixman_fill_mmx(ptr nocapture %bits, i32 %stride, i32 %bpp, i32 %x, i32 %y, i32 %width, i32 %height, i32 %xor) nounwind ssp {
99
entry:
1010
%conv = zext i32 %xor to i64
1111
%shl = shl nuw i64 %conv, 32
1212
%or = or i64 %shl, %conv
13-
%0 = bitcast i64 %or to x86_mmx
13+
%0 = bitcast i64 %or to <1 x i64>
1414
; CHECK: movq [[MMXR:%mm[0-7],]] {{%mm[0-7]}}
1515
; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
1616
; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
1717
; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
1818
; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
1919
; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
2020
; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}}
21-
%1 = tail call %0 asm "movq\09\09$7,\09$0\0Amovq\09\09$7,\09$1\0Amovq\09\09$7,\09$2\0Amovq\09\09$7,\09$3\0Amovq\09\09$7,\09$4\0Amovq\09\09$7,\09$5\0Amovq\09\09$7,\09$6\0A", "=&y,=&y,=&y,=&y,=&y,=&y,=y,y,~{dirflag},~{fpsr},~{flags}"(x86_mmx %0) nounwind, !srcloc !0
21+
%1 = tail call %0 asm "movq\09\09$7,\09$0\0Amovq\09\09$7,\09$1\0Amovq\09\09$7,\09$2\0Amovq\09\09$7,\09$3\0Amovq\09\09$7,\09$4\0Amovq\09\09$7,\09$5\0Amovq\09\09$7,\09$6\0A", "=&y,=&y,=&y,=&y,=&y,=&y,=y,y,~{dirflag},~{fpsr},~{flags}"(<1 x i64> %0) nounwind, !srcloc !0
2222
%asmresult = extractvalue %0 %1, 0
2323
%asmresult6 = extractvalue %0 %1, 1
2424
%asmresult7 = extractvalue %0 %1, 2
@@ -34,7 +34,7 @@ entry:
3434
; CHECK-NEXT: movq {{%mm[0-7]}},
3535
; CHECK-NEXT: movq {{%mm[0-7]}},
3636
; CHECK-NEXT: movq {{%mm[0-7]}},
37-
tail call void asm sideeffect "movq\09$1,\09 ($0)\0Amovq\09$2,\09 8($0)\0Amovq\09$3,\0916($0)\0Amovq\09$4,\0924($0)\0Amovq\09$5,\0932($0)\0Amovq\09$6,\0940($0)\0Amovq\09$7,\0948($0)\0Amovq\09$8,\0956($0)\0A", "r,y,y,y,y,y,y,y,y,~{memory},~{dirflag},~{fpsr},~{flags}"(ptr undef, x86_mmx %0, x86_mmx %asmresult, x86_mmx %asmresult6, x86_mmx %asmresult7, x86_mmx %asmresult8, x86_mmx %asmresult9, x86_mmx %asmresult10, x86_mmx %asmresult11) nounwind, !srcloc !1
37+
tail call void asm sideeffect "movq\09$1,\09 ($0)\0Amovq\09$2,\09 8($0)\0Amovq\09$3,\0916($0)\0Amovq\09$4,\0924($0)\0Amovq\09$5,\0932($0)\0Amovq\09$6,\0940($0)\0Amovq\09$7,\0948($0)\0Amovq\09$8,\0956($0)\0A", "r,y,y,y,y,y,y,y,y,~{memory},~{dirflag},~{fpsr},~{flags}"(ptr undef, <1 x i64> %0, <1 x i64> %asmresult, <1 x i64> %asmresult6, <1 x i64> %asmresult7, <1 x i64> %asmresult8, <1 x i64> %asmresult9, <1 x i64> %asmresult10, <1 x i64> %asmresult11) nounwind, !srcloc !1
3838
tail call void @llvm.x86.mmx.emms() nounwind
3939
ret i32 1
4040
}

‎llvm/test/CodeGen/X86/avx-vbroadcast.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -1011,7 +1011,7 @@ define float @broadcast_lifetime() nounwind {
10111011
ret float %7
10121012
}
10131013

1014-
define <8 x i16> @broadcast_x86_mmx(x86_mmx %tmp) nounwind {
1014+
define <8 x i16> @broadcast_x86_mmx(<1 x i64> %tmp) nounwind {
10151015
; X86-LABEL: broadcast_x86_mmx:
10161016
; X86: ## %bb.0: ## %bb
10171017
; X86-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
@@ -1023,7 +1023,7 @@ define <8 x i16> @broadcast_x86_mmx(x86_mmx %tmp) nounwind {
10231023
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
10241024
; X64-NEXT: retq
10251025
bb:
1026-
%tmp1 = bitcast x86_mmx %tmp to i64
1026+
%tmp1 = bitcast <1 x i64> %tmp to i64
10271027
%tmp2 = insertelement <2 x i64> undef, i64 %tmp1, i32 0
10281028
%tmp3 = bitcast <2 x i64> %tmp2 to <8 x i16>
10291029
%tmp4 = shufflevector <8 x i16> %tmp3, <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>

‎llvm/test/CodeGen/X86/avx2-vbroadcast.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -1449,7 +1449,7 @@ eintry:
14491449
ret void
14501450
}
14511451

1452-
define <8 x i16> @broadcast_x86_mmx(x86_mmx %tmp) nounwind {
1452+
define <8 x i16> @broadcast_x86_mmx(<1 x i64> %tmp) nounwind {
14531453
; X86-LABEL: broadcast_x86_mmx:
14541454
; X86: ## %bb.0: ## %bb
14551455
; X86-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
@@ -1466,7 +1466,7 @@ define <8 x i16> @broadcast_x86_mmx(x86_mmx %tmp) nounwind {
14661466
; X64-AVX512VL-NEXT: vpbroadcastq %rdi, %xmm0
14671467
; X64-AVX512VL-NEXT: retq
14681468
bb:
1469-
%tmp1 = bitcast x86_mmx %tmp to i64
1469+
%tmp1 = bitcast <1 x i64> %tmp to i64
14701470
%tmp2 = insertelement <2 x i64> undef, i64 %tmp1, i32 0
14711471
%tmp3 = bitcast <2 x i64> %tmp2 to <8 x i16>
14721472
%tmp4 = shufflevector <8 x i16> %tmp3, <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>

‎llvm/test/CodeGen/X86/bitcast-mmx.ll

+17-17
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,9 @@ define i32 @t0(i64 %x) nounwind {
1717
; X64-NEXT: retq
1818
entry:
1919
%0 = bitcast i64 %x to <4 x i16>
20-
%1 = bitcast <4 x i16> %0 to x86_mmx
21-
%2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -18)
22-
%3 = bitcast x86_mmx %2 to <4 x i16>
20+
%1 = bitcast <4 x i16> %0 to <1 x i64>
21+
%2 = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> %1, i8 -18)
22+
%3 = bitcast <1 x i64> %2 to <4 x i16>
2323
%4 = bitcast <4 x i16> %3 to <1 x i64>
2424
%5 = extractelement <1 x i64> %4, i32 0
2525
%6 = bitcast i64 %5 to <2 x i32>
@@ -52,9 +52,9 @@ define i64 @t1(i64 %x, i32 %n) nounwind {
5252
; X64-NEXT: movq %mm0, %rax
5353
; X64-NEXT: retq
5454
entry:
55-
%0 = bitcast i64 %x to x86_mmx
56-
%1 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %0, i32 %n)
57-
%2 = bitcast x86_mmx %1 to i64
55+
%0 = bitcast i64 %x to <1 x i64>
56+
%1 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %0, i32 %n)
57+
%2 = bitcast <1 x i64> %1 to i64
5858
ret i64 %2
5959
}
6060

@@ -88,11 +88,11 @@ define i64 @t2(i64 %x, i32 %n, i32 %w) nounwind {
8888
entry:
8989
%0 = insertelement <2 x i32> undef, i32 %w, i32 0
9090
%1 = insertelement <2 x i32> %0, i32 0, i32 1
91-
%2 = bitcast <2 x i32> %1 to x86_mmx
92-
%3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %2, i32 %n)
93-
%4 = bitcast i64 %x to x86_mmx
94-
%5 = tail call x86_mmx @llvm.x86.mmx.por(x86_mmx %4, x86_mmx %3)
95-
%6 = bitcast x86_mmx %5 to i64
91+
%2 = bitcast <2 x i32> %1 to <1 x i64>
92+
%3 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %2, i32 %n)
93+
%4 = bitcast i64 %x to <1 x i64>
94+
%5 = tail call <1 x i64> @llvm.x86.mmx.por(<1 x i64> %4, <1 x i64> %3)
95+
%6 = bitcast <1 x i64> %5 to i64
9696
ret i64 %6
9797
}
9898

@@ -123,14 +123,14 @@ define i64 @t3(ptr %y, ptr %n) nounwind {
123123
; X64-NEXT: movq %mm0, %rax
124124
; X64-NEXT: retq
125125
entry:
126-
%0 = load x86_mmx, ptr %y, align 8
126+
%0 = load <1 x i64>, ptr %y, align 8
127127
%1 = load i32, ptr %n, align 4
128-
%2 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %0, i32 %1)
129-
%3 = bitcast x86_mmx %2 to i64
128+
%2 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %0, i32 %1)
129+
%3 = bitcast <1 x i64> %2 to i64
130130
ret i64 %3
131131
}
132132

133-
declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
134-
declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
135-
declare x86_mmx @llvm.x86.mmx.por(x86_mmx, x86_mmx)
133+
declare <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64>, i8)
134+
declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32)
135+
declare <1 x i64> @llvm.x86.mmx.por(<1 x i64>, <1 x i64>)
136136

‎llvm/test/CodeGen/X86/expand-vr64-gr64-copy.mir

+3-3
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,9 @@
66

77
define <2 x i32> @test_paddw(<2 x i32> %a) nounwind readnone {
88
entry:
9-
%0 = bitcast <2 x i32> %a to x86_mmx
10-
%1 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %0, x86_mmx %0)
11-
%2 = bitcast x86_mmx %1 to <2 x i32>
9+
%0 = bitcast <2 x i32> %a to <1 x i64>
10+
%1 = tail call <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64> %0, <1 x i64> %0)
11+
%2 = bitcast <1 x i64> %1 to <2 x i32>
1212
ret <2 x i32> %2
1313
}
1414

‎llvm/test/CodeGen/X86/fast-isel-bc.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44

55
; PR4684
66

7-
declare void @func2(x86_mmx)
7+
declare void @func2(<1 x i64>)
88

99
; This isn't spectacular, but it's MMX code at -O0...
1010

@@ -28,7 +28,7 @@ define void @func1() nounwind {
2828
; X64-NEXT: callq _func2
2929
; X64-NEXT: popq %rax
3030
; X64-NEXT: retq
31-
%tmp0 = bitcast <2 x i32> <i32 0, i32 2> to x86_mmx
32-
call void @func2(x86_mmx %tmp0)
31+
%tmp0 = bitcast <2 x i32> <i32 0, i32 2> to <1 x i64>
32+
call void @func2(<1 x i64> %tmp0)
3333
ret void
3434
}

‎llvm/test/CodeGen/X86/fast-isel-nontemporal.ll

+4-4
Original file line numberDiff line numberDiff line change
@@ -104,12 +104,12 @@ define void @test_mmx(ptr nocapture %a0, ptr nocapture %a1) {
104104
; ALL-NEXT: movntq %mm0, (%rsi)
105105
; ALL-NEXT: retq
106106
entry:
107-
%0 = load x86_mmx, ptr %a0
108-
%1 = call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %0, i32 3)
109-
store x86_mmx %1, ptr %a1, align 8, !nontemporal !1
107+
%0 = load <1 x i64>, ptr %a0
108+
%1 = call <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64> %0, i32 3)
109+
store <1 x i64> %1, ptr %a1, align 8, !nontemporal !1
110110
ret void
111111
}
112-
declare x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx, i32) nounwind readnone
112+
declare <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64>, i32) nounwind readnone
113113

114114
;
115115
; 128-bit Vector Stores

‎llvm/test/CodeGen/X86/mmx-arg-passing-x86-64.ll

+7-7
Original file line numberDiff line numberDiff line change
@@ -14,12 +14,12 @@ define void @t3() nounwind {
1414
; X86-64-NEXT: xorl %eax, %eax
1515
; X86-64-NEXT: jmp _pass_v8qi ## TAILCALL
1616
%tmp3 = load <8 x i8>, ptr @g_v8qi, align 8
17-
%tmp3a = bitcast <8 x i8> %tmp3 to x86_mmx
18-
%tmp4 = tail call i32 (...) @pass_v8qi( x86_mmx %tmp3a ) nounwind
17+
%tmp3a = bitcast <8 x i8> %tmp3 to <1 x i64>
18+
%tmp4 = tail call i32 (...) @pass_v8qi( <1 x i64> %tmp3a ) nounwind
1919
ret void
2020
}
2121

22-
define void @t4(x86_mmx %v1, x86_mmx %v2) nounwind {
22+
define void @t4(<1 x i64> %v1, <1 x i64> %v2) nounwind {
2323
; X86-64-LABEL: t4:
2424
; X86-64: ## %bb.0:
2525
; X86-64-NEXT: movq %rdi, %xmm0
@@ -28,11 +28,11 @@ define void @t4(x86_mmx %v1, x86_mmx %v2) nounwind {
2828
; X86-64-NEXT: movq %xmm1, %rdi
2929
; X86-64-NEXT: xorl %eax, %eax
3030
; X86-64-NEXT: jmp _pass_v8qi ## TAILCALL
31-
%v1a = bitcast x86_mmx %v1 to <8 x i8>
32-
%v2b = bitcast x86_mmx %v2 to <8 x i8>
31+
%v1a = bitcast <1 x i64> %v1 to <8 x i8>
32+
%v2b = bitcast <1 x i64> %v2 to <8 x i8>
3333
%tmp3 = add <8 x i8> %v1a, %v2b
34-
%tmp3a = bitcast <8 x i8> %tmp3 to x86_mmx
35-
%tmp4 = tail call i32 (...) @pass_v8qi( x86_mmx %tmp3a ) nounwind
34+
%tmp3a = bitcast <8 x i8> %tmp3 to <1 x i64>
35+
%tmp4 = tail call i32 (...) @pass_v8qi( <1 x i64> %tmp3a ) nounwind
3636
ret void
3737
}
3838

‎llvm/test/CodeGen/X86/mmx-arg-passing.ll

+5-6
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,9 @@
88
; On Darwin x86-64, v8i8, v4i16, v2i32 values are passed in XMM[0-7].
99
; On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
1010

11-
@u1 = external global x86_mmx
11+
@u1 = external global <1 x i64>
1212

13-
define void @t1(x86_mmx %v1) nounwind {
13+
define void @t1(<1 x i64> %v1) nounwind {
1414
; X86-32-LABEL: t1:
1515
; X86-32: ## %bb.0:
1616
; X86-32-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -25,11 +25,11 @@ define void @t1(x86_mmx %v1) nounwind {
2525
; X86-64-NEXT: movq _u1@GOTPCREL(%rip), %rax
2626
; X86-64-NEXT: movq %rdi, (%rax)
2727
; X86-64-NEXT: retq
28-
store x86_mmx %v1, ptr @u1, align 8
28+
store <1 x i64> %v1, ptr @u1, align 8
2929
ret void
3030
}
3131

32-
@u2 = external global x86_mmx
32+
@u2 = external global <1 x i64>
3333

3434
define void @t2(<1 x i64> %v1) nounwind {
3535
; X86-32-LABEL: t2:
@@ -46,7 +46,6 @@ define void @t2(<1 x i64> %v1) nounwind {
4646
; X86-64-NEXT: movq _u2@GOTPCREL(%rip), %rax
4747
; X86-64-NEXT: movq %rdi, (%rax)
4848
; X86-64-NEXT: retq
49-
%tmp = bitcast <1 x i64> %v1 to x86_mmx
50-
store x86_mmx %tmp, ptr @u2, align 8
49+
store <1 x i64> %v1, ptr @u2, align 8
5150
ret void
5251
}

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