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[VPlan] Don't convert widen recipes to VP intrinsics in EVL transform
1 parent 20637e7 commit b71d001

23 files changed

+150
-263
lines changed

‎llvm/lib/Transforms/Vectorize/VPlan.h

Lines changed: 1 addition & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -523,7 +523,6 @@ class VPSingleDefRecipe : public VPRecipeBase, public VPValue {
523523
case VPRecipeBase::VPWidenGEPSC:
524524
case VPRecipeBase::VPWidenIntrinsicSC:
525525
case VPRecipeBase::VPWidenSC:
526-
case VPRecipeBase::VPWidenEVLSC:
527526
case VPRecipeBase::VPWidenSelectSC:
528527
case VPRecipeBase::VPBlendSC:
529528
case VPRecipeBase::VPPredInstPHISC:
@@ -710,7 +709,6 @@ class VPRecipeWithIRFlags : public VPSingleDefRecipe {
710709
static inline bool classof(const VPRecipeBase *R) {
711710
return R->getVPDefID() == VPRecipeBase::VPInstructionSC ||
712711
R->getVPDefID() == VPRecipeBase::VPWidenSC ||
713-
R->getVPDefID() == VPRecipeBase::VPWidenEVLSC ||
714712
R->getVPDefID() == VPRecipeBase::VPWidenGEPSC ||
715713
R->getVPDefID() == VPRecipeBase::VPWidenCastSC ||
716714
R->getVPDefID() == VPRecipeBase::VPWidenIntrinsicSC ||
@@ -1116,8 +1114,7 @@ class VPWidenRecipe : public VPRecipeWithIRFlags {
11161114
}
11171115

11181116
static inline bool classof(const VPRecipeBase *R) {
1119-
return R->getVPDefID() == VPRecipeBase::VPWidenSC ||
1120-
R->getVPDefID() == VPRecipeBase::VPWidenEVLSC;
1117+
return R->getVPDefID() == VPRecipeBase::VPWidenSC;
11211118
}
11221119

11231120
static inline bool classof(const VPUser *U) {
@@ -1142,54 +1139,6 @@ class VPWidenRecipe : public VPRecipeWithIRFlags {
11421139
#endif
11431140
};
11441141

1145-
/// A recipe for widening operations with vector-predication intrinsics with
1146-
/// explicit vector length (EVL).
1147-
class VPWidenEVLRecipe : public VPWidenRecipe {
1148-
using VPRecipeWithIRFlags::transferFlags;
1149-
1150-
public:
1151-
template <typename IterT>
1152-
VPWidenEVLRecipe(Instruction &I, iterator_range<IterT> Operands, VPValue &EVL)
1153-
: VPWidenRecipe(VPDef::VPWidenEVLSC, I, Operands) {
1154-
addOperand(&EVL);
1155-
}
1156-
VPWidenEVLRecipe(VPWidenRecipe &W, VPValue &EVL)
1157-
: VPWidenEVLRecipe(*W.getUnderlyingInstr(), W.operands(), EVL) {
1158-
transferFlags(W);
1159-
}
1160-
1161-
~VPWidenEVLRecipe() override = default;
1162-
1163-
VPWidenRecipe *clone() override final {
1164-
llvm_unreachable("VPWidenEVLRecipe cannot be cloned");
1165-
return nullptr;
1166-
}
1167-
1168-
VP_CLASSOF_IMPL(VPDef::VPWidenEVLSC);
1169-
1170-
VPValue *getEVL() { return getOperand(getNumOperands() - 1); }
1171-
const VPValue *getEVL() const { return getOperand(getNumOperands() - 1); }
1172-
1173-
/// Produce a vp-intrinsic using the opcode and operands of the recipe,
1174-
/// processing EVL elements.
1175-
void execute(VPTransformState &State) override final;
1176-
1177-
/// Returns true if the recipe only uses the first lane of operand \p Op.
1178-
bool onlyFirstLaneUsed(const VPValue *Op) const override {
1179-
assert(is_contained(operands(), Op) &&
1180-
"Op must be an operand of the recipe");
1181-
// EVL in that recipe is always the last operand, thus any use before means
1182-
// the VPValue should be vectorized.
1183-
return getEVL() == Op;
1184-
}
1185-
1186-
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1187-
/// Print the recipe.
1188-
void print(raw_ostream &O, const Twine &Indent,
1189-
VPSlotTracker &SlotTracker) const override final;
1190-
#endif
1191-
};
1192-
11931142
/// VPWidenCastRecipe is a recipe to create vector cast instructions.
11941143
class VPWidenCastRecipe : public VPRecipeWithIRFlags {
11951144
/// Cast instruction opcode.

‎llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -245,9 +245,8 @@ Type *VPTypeAnalysis::inferScalarType(const VPValue *V) {
245245
VPPartialReductionRecipe>([this](const VPRecipeBase *R) {
246246
return inferScalarType(R->getOperand(0));
247247
})
248-
.Case<VPBlendRecipe, VPInstruction, VPWidenRecipe, VPWidenEVLRecipe,
249-
VPReplicateRecipe, VPWidenCallRecipe, VPWidenMemoryRecipe,
250-
VPWidenSelectRecipe>(
248+
.Case<VPBlendRecipe, VPInstruction, VPWidenRecipe, VPReplicateRecipe,
249+
VPWidenCallRecipe, VPWidenMemoryRecipe, VPWidenSelectRecipe>(
251250
[this](const auto *R) { return inferScalarTypeForRecipe(R); })
252251
.Case<VPWidenIntrinsicRecipe>([](const VPWidenIntrinsicRecipe *R) {
253252
return R->getResultType();

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

Lines changed: 0 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,6 @@ bool VPRecipeBase::mayWriteToMemory() const {
8585
case VPWidenLoadSC:
8686
case VPWidenPHISC:
8787
case VPWidenSC:
88-
case VPWidenEVLSC:
8988
case VPWidenSelectSC: {
9089
const Instruction *I =
9190
dyn_cast_or_null<Instruction>(getVPSingleValue()->getUnderlyingValue());
@@ -131,7 +130,6 @@ bool VPRecipeBase::mayReadFromMemory() const {
131130
case VPWidenIntOrFpInductionSC:
132131
case VPWidenPHISC:
133132
case VPWidenSC:
134-
case VPWidenEVLSC:
135133
case VPWidenSelectSC: {
136134
const Instruction *I =
137135
dyn_cast_or_null<Instruction>(getVPSingleValue()->getUnderlyingValue());
@@ -172,7 +170,6 @@ bool VPRecipeBase::mayHaveSideEffects() const {
172170
case VPWidenPHISC:
173171
case VPWidenPointerInductionSC:
174172
case VPWidenSC:
175-
case VPWidenEVLSC:
176173
case VPWidenSelectSC: {
177174
const Instruction *I =
178175
dyn_cast_or_null<Instruction>(getVPSingleValue()->getUnderlyingValue());
@@ -1550,42 +1547,6 @@ InstructionCost VPWidenRecipe::computeCost(ElementCount VF,
15501547
}
15511548
}
15521549

1553-
void VPWidenEVLRecipe::execute(VPTransformState &State) {
1554-
unsigned Opcode = getOpcode();
1555-
// TODO: Support other opcodes
1556-
if (!Instruction::isBinaryOp(Opcode) && !Instruction::isUnaryOp(Opcode))
1557-
llvm_unreachable("Unsupported opcode in VPWidenEVLRecipe::execute");
1558-
1559-
State.setDebugLocFrom(getDebugLoc());
1560-
1561-
assert(State.get(getOperand(0))->getType()->isVectorTy() &&
1562-
"VPWidenEVLRecipe should not be used for scalars");
1563-
1564-
VPValue *EVL = getEVL();
1565-
Value *EVLArg = State.get(EVL, /*NeedsScalar=*/true);
1566-
IRBuilderBase &BuilderIR = State.Builder;
1567-
VectorBuilder Builder(BuilderIR);
1568-
Value *Mask = BuilderIR.CreateVectorSplat(State.VF, BuilderIR.getTrue());
1569-
1570-
SmallVector<Value *, 4> Ops;
1571-
for (unsigned I = 0, E = getNumOperands() - 1; I < E; ++I) {
1572-
VPValue *VPOp = getOperand(I);
1573-
Ops.push_back(State.get(VPOp));
1574-
}
1575-
1576-
Builder.setMask(Mask).setEVL(EVLArg);
1577-
Value *VPInst =
1578-
Builder.createVectorInstruction(Opcode, Ops[0]->getType(), Ops, "vp.op");
1579-
// Currently vp-intrinsics only accept FMF flags.
1580-
// TODO: Enable other flags when support is added.
1581-
if (isa<FPMathOperator>(VPInst))
1582-
setFlags(cast<Instruction>(VPInst));
1583-
1584-
State.set(this, VPInst);
1585-
State.addMetadata(VPInst,
1586-
dyn_cast_or_null<Instruction>(getUnderlyingValue()));
1587-
}
1588-
15891550
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
15901551
void VPWidenRecipe::print(raw_ostream &O, const Twine &Indent,
15911552
VPSlotTracker &SlotTracker) const {
@@ -1595,15 +1556,6 @@ void VPWidenRecipe::print(raw_ostream &O, const Twine &Indent,
15951556
printFlags(O);
15961557
printOperands(O, SlotTracker);
15971558
}
1598-
1599-
void VPWidenEVLRecipe::print(raw_ostream &O, const Twine &Indent,
1600-
VPSlotTracker &SlotTracker) const {
1601-
O << Indent << "WIDEN ";
1602-
printAsOperand(O, SlotTracker);
1603-
O << " = vp." << Instruction::getOpcodeName(getOpcode());
1604-
printFlags(O);
1605-
printOperands(O, SlotTracker);
1606-
}
16071559
#endif
16081560

16091561
void VPWidenCastRecipe::execute(VPTransformState &State) {

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp

Lines changed: 0 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -1665,40 +1665,10 @@ static VPRecipeBase *createEVLRecipe(VPValue *HeaderMask,
16651665
VPValue *NewMask = GetNewMask(S->getMask());
16661666
return new VPWidenStoreEVLRecipe(*S, EVL, NewMask);
16671667
})
1668-
.Case<VPWidenRecipe>([&](VPWidenRecipe *W) -> VPRecipeBase * {
1669-
unsigned Opcode = W->getOpcode();
1670-
if (!Instruction::isBinaryOp(Opcode) && !Instruction::isUnaryOp(Opcode))
1671-
return nullptr;
1672-
return new VPWidenEVLRecipe(*W, EVL);
1673-
})
16741668
.Case<VPReductionRecipe>([&](VPReductionRecipe *Red) {
16751669
VPValue *NewMask = GetNewMask(Red->getCondOp());
16761670
return new VPReductionEVLRecipe(*Red, EVL, NewMask);
16771671
})
1678-
.Case<VPWidenIntrinsicRecipe, VPWidenCastRecipe>(
1679-
[&](auto *CR) -> VPRecipeBase * {
1680-
Intrinsic::ID VPID;
1681-
if (auto *CallR = dyn_cast<VPWidenIntrinsicRecipe>(CR)) {
1682-
VPID =
1683-
VPIntrinsic::getForIntrinsic(CallR->getVectorIntrinsicID());
1684-
} else {
1685-
auto *CastR = cast<VPWidenCastRecipe>(CR);
1686-
VPID = VPIntrinsic::getForOpcode(CastR->getOpcode());
1687-
}
1688-
1689-
// Not all intrinsics have a corresponding VP intrinsic.
1690-
if (VPID == Intrinsic::not_intrinsic)
1691-
return nullptr;
1692-
assert(VPIntrinsic::getMaskParamPos(VPID) &&
1693-
VPIntrinsic::getVectorLengthParamPos(VPID) &&
1694-
"Expected VP intrinsic to have mask and EVL");
1695-
1696-
SmallVector<VPValue *> Ops(CR->operands());
1697-
Ops.push_back(&AllOneMask);
1698-
Ops.push_back(&EVL);
1699-
return new VPWidenIntrinsicRecipe(
1700-
VPID, Ops, TypeInfo.inferScalarType(CR), CR->getDebugLoc());
1701-
})
17021672
.Case<VPWidenSelectRecipe>([&](VPWidenSelectRecipe *Sel) {
17031673
SmallVector<VPValue *> Ops(Sel->operands());
17041674
Ops.push_back(&EVL);

‎llvm/lib/Transforms/Vectorize/VPlanValue.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -351,7 +351,6 @@ class VPDef {
351351
VPWidenStoreEVLSC,
352352
VPWidenStoreSC,
353353
VPWidenSC,
354-
VPWidenEVLSC,
355354
VPWidenSelectSC,
356355
VPBlendSC,
357356
VPHistogramSC,

‎llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -145,10 +145,6 @@ bool VPlanVerifier::verifyEVLRecipe(const VPInstruction &EVL) const {
145145
[&](const VPRecipeBase *S) { return VerifyEVLUse(*S, 2); })
146146
.Case<VPWidenLoadEVLRecipe, VPReverseVectorPointerRecipe>(
147147
[&](const VPRecipeBase *R) { return VerifyEVLUse(*R, 1); })
148-
.Case<VPWidenEVLRecipe>([&](const VPWidenEVLRecipe *W) {
149-
return VerifyEVLUse(*W,
150-
Instruction::isUnaryOp(W->getOpcode()) ? 1 : 2);
151-
})
152148
.Case<VPScalarCastRecipe>(
153149
[&](const VPScalarCastRecipe *S) { return VerifyEVLUse(*S, 0); })
154150
.Case<VPInstruction>([&](const VPInstruction *I) {

‎llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -143,8 +143,8 @@ define i32 @add_i16_i32(ptr nocapture readonly %x, i32 %n) {
143143
; IF-EVL-OUTLOOP-NEXT: [[TMP7:%.*]] = getelementptr inbounds i16, ptr [[X:%.*]], i32 [[TMP6]]
144144
; IF-EVL-OUTLOOP-NEXT: [[TMP8:%.*]] = getelementptr inbounds i16, ptr [[TMP7]], i32 0
145145
; IF-EVL-OUTLOOP-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i16> @llvm.vp.load.nxv4i16.p0(ptr align 2 [[TMP8]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP5]])
146-
; IF-EVL-OUTLOOP-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i32> @llvm.vp.sext.nxv4i32.nxv4i16(<vscale x 4 x i16> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP5]])
147-
; IF-EVL-OUTLOOP-NEXT: [[VP_OP:%.*]] = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 4 x i32> [[TMP9]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP5]])
146+
; IF-EVL-OUTLOOP-NEXT: [[TMP9:%.*]] = sext <vscale x 4 x i16> [[VP_OP_LOAD]] to <vscale x 4 x i32>
147+
; IF-EVL-OUTLOOP-NEXT: [[VP_OP:%.*]] = add <vscale x 4 x i32> [[VEC_PHI]], [[TMP9]]
148148
; IF-EVL-OUTLOOP-NEXT: [[TMP10]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[VP_OP]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP5]])
149149
; IF-EVL-OUTLOOP-NEXT: [[INDEX_EVL_NEXT]] = add nuw i32 [[TMP5]], [[EVL_BASED_IV]]
150150
; IF-EVL-OUTLOOP-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], [[TMP4]]
@@ -200,7 +200,7 @@ define i32 @add_i16_i32(ptr nocapture readonly %x, i32 %n) {
200200
; IF-EVL-INLOOP-NEXT: [[TMP8:%.*]] = getelementptr inbounds i16, ptr [[X:%.*]], i32 [[TMP7]]
201201
; IF-EVL-INLOOP-NEXT: [[TMP9:%.*]] = getelementptr inbounds i16, ptr [[TMP8]], i32 0
202202
; IF-EVL-INLOOP-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 8 x i16> @llvm.vp.load.nxv8i16.p0(ptr align 2 [[TMP9]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP6]])
203-
; IF-EVL-INLOOP-NEXT: [[TMP14:%.*]] = call <vscale x 8 x i32> @llvm.vp.sext.nxv8i32.nxv8i16(<vscale x 8 x i16> [[VP_OP_LOAD]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP6]])
203+
; IF-EVL-INLOOP-NEXT: [[TMP14:%.*]] = sext <vscale x 8 x i16> [[VP_OP_LOAD]] to <vscale x 8 x i32>
204204
; IF-EVL-INLOOP-NEXT: [[TMP10:%.*]] = call i32 @llvm.vp.reduce.add.nxv8i32(i32 0, <vscale x 8 x i32> [[TMP14]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP6]])
205205
; IF-EVL-INLOOP-NEXT: [[TMP11]] = add i32 [[TMP10]], [[VEC_PHI]]
206206
; IF-EVL-INLOOP-NEXT: [[INDEX_EVL_NEXT]] = add nuw i32 [[TMP6]], [[EVL_BASED_IV]]

‎llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -27,10 +27,10 @@ define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr %src) {
2727
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP4]]
2828
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP5]], i32 0
2929
; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 1 x i8> @llvm.vp.load.nxv1i8.p0(ptr align 1 [[TMP6]], <vscale x 1 x i1> splat (i1 true), i32 [[TMP3]])
30-
; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 1 x i16> @llvm.vp.zext.nxv1i16.nxv1i8(<vscale x 1 x i8> [[VP_OP_LOAD]], <vscale x 1 x i1> splat (i1 true), i32 [[TMP3]])
31-
; CHECK-NEXT: [[VP_OP:%.*]] = call <vscale x 1 x i16> @llvm.vp.mul.nxv1i16(<vscale x 1 x i16> zeroinitializer, <vscale x 1 x i16> [[TMP7]], <vscale x 1 x i1> splat (i1 true), i32 [[TMP3]])
32-
; CHECK-NEXT: [[VP_OP1:%.*]] = call <vscale x 1 x i16> @llvm.vp.lshr.nxv1i16(<vscale x 1 x i16> [[VP_OP]], <vscale x 1 x i16> trunc (<vscale x 1 x i32> splat (i32 1) to <vscale x 1 x i16>), <vscale x 1 x i1> splat (i1 true), i32 [[TMP3]])
33-
; CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 1 x i8> @llvm.vp.trunc.nxv1i8.nxv1i16(<vscale x 1 x i16> [[VP_OP1]], <vscale x 1 x i1> splat (i1 true), i32 [[TMP3]])
30+
; CHECK-NEXT: [[TMP7:%.*]] = zext <vscale x 1 x i8> [[VP_OP_LOAD]] to <vscale x 1 x i16>
31+
; CHECK-NEXT: [[TMP12:%.*]] = mul <vscale x 1 x i16> zeroinitializer, [[TMP7]]
32+
; CHECK-NEXT: [[VP_OP1:%.*]] = lshr <vscale x 1 x i16> [[TMP12]], trunc (<vscale x 1 x i32> splat (i32 1) to <vscale x 1 x i16>)
33+
; CHECK-NEXT: [[TMP8:%.*]] = trunc <vscale x 1 x i16> [[VP_OP1]] to <vscale x 1 x i8>
3434
; CHECK-NEXT: call void @llvm.vp.scatter.nxv1i8.nxv1p0(<vscale x 1 x i8> [[TMP8]], <vscale x 1 x ptr> align 1 zeroinitializer, <vscale x 1 x i1> splat (i1 true), i32 [[TMP3]])
3535
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP3]] to i64
3636
; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP9]], [[EVL_BASED_IV]]

‎llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -44,15 +44,15 @@ define void @type_info_cache_clobber(ptr %dstv, ptr %src, i64 %wide.trip.count)
4444
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP12]]
4545
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[TMP13]], i32 0
4646
; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 8 x i8> @llvm.vp.load.nxv8i8.p0(ptr align 1 [[TMP14]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP11]]), !alias.scope [[META0:![0-9]+]]
47-
; CHECK-NEXT: [[TMP15:%.*]] = call <vscale x 8 x i32> @llvm.vp.zext.nxv8i32.nxv8i8(<vscale x 8 x i8> [[VP_OP_LOAD]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP11]])
48-
; CHECK-NEXT: [[VP_OP:%.*]] = call <vscale x 8 x i32> @llvm.vp.mul.nxv8i32(<vscale x 8 x i32> [[TMP15]], <vscale x 8 x i32> zeroinitializer, <vscale x 8 x i1> splat (i1 true), i32 [[TMP11]])
49-
; CHECK-NEXT: [[VP_OP2:%.*]] = call <vscale x 8 x i32> @llvm.vp.ashr.nxv8i32(<vscale x 8 x i32> [[TMP15]], <vscale x 8 x i32> zeroinitializer, <vscale x 8 x i1> splat (i1 true), i32 [[TMP11]])
50-
; CHECK-NEXT: [[VP_OP3:%.*]] = call <vscale x 8 x i32> @llvm.vp.or.nxv8i32(<vscale x 8 x i32> [[VP_OP2]], <vscale x 8 x i32> zeroinitializer, <vscale x 8 x i1> splat (i1 true), i32 [[TMP11]])
47+
; CHECK-NEXT: [[TMP15:%.*]] = zext <vscale x 8 x i8> [[VP_OP_LOAD]] to <vscale x 8 x i32>
48+
; CHECK-NEXT: [[VP_OP:%.*]] = mul <vscale x 8 x i32> [[TMP15]], zeroinitializer
49+
; CHECK-NEXT: [[TMP23:%.*]] = ashr <vscale x 8 x i32> [[TMP15]], zeroinitializer
50+
; CHECK-NEXT: [[VP_OP3:%.*]] = or <vscale x 8 x i32> [[TMP23]], zeroinitializer
5151
; CHECK-NEXT: [[TMP16:%.*]] = icmp ult <vscale x 8 x i32> [[TMP15]], zeroinitializer
5252
; CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 8 x i32> @llvm.vp.select.nxv8i32(<vscale x 8 x i1> [[TMP16]], <vscale x 8 x i32> [[VP_OP3]], <vscale x 8 x i32> zeroinitializer, i32 [[TMP11]])
53-
; CHECK-NEXT: [[TMP18:%.*]] = call <vscale x 8 x i8> @llvm.vp.trunc.nxv8i8.nxv8i32(<vscale x 8 x i32> [[TMP17]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP11]])
54-
; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i8.nxv8p0(<vscale x 8 x i8> [[TMP18]], <vscale x 8 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP11]]), !alias.scope [[META3:![0-9]+]], !noalias [[META0]]
55-
; CHECK-NEXT: [[TMP19:%.*]] = call <vscale x 8 x i16> @llvm.vp.trunc.nxv8i16.nxv8i32(<vscale x 8 x i32> [[VP_OP]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP11]])
53+
; CHECK-NEXT: [[TMP24:%.*]] = trunc <vscale x 8 x i32> [[TMP17]] to <vscale x 8 x i8>
54+
; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i8.nxv8p0(<vscale x 8 x i8> [[TMP24]], <vscale x 8 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP11]]), !alias.scope [[META3:![0-9]+]], !noalias [[META0]]
55+
; CHECK-NEXT: [[TMP19:%.*]] = trunc <vscale x 8 x i32> [[VP_OP]] to <vscale x 8 x i16>
5656
; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> [[TMP19]], <vscale x 8 x ptr> align 2 zeroinitializer, <vscale x 8 x i1> splat (i1 true), i32 [[TMP11]])
5757
; CHECK-NEXT: [[TMP20:%.*]] = zext i32 [[TMP11]] to i64
5858
; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP20]], [[EVL_BASED_IV]]

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