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[X86] ReplaceNodeResults - adjust assert to allow XOP or GFNI subtargets to split i64 BITREVERSE nodes on 32-bit targets
Fixes #113353 Fixes #113034
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llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -34158,9 +34158,9 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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}
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case ISD::BITREVERSE: {
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assert(N->getValueType(0) == MVT::i64 && "Unexpected VT!");
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assert(Subtarget.hasXOP() && "Expected XOP");
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// We can use VPPERM by copying to a vector register and back. We'll need
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// to move the scalar in two i32 pieces.
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assert((Subtarget.hasXOP() || Subtarget.hasGFNI()) && "Expected XOP/GFNI");
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// We can use VPPERM/GF2P8AFFINEQB by copying to a vector register and back.
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// We'll need to move the scalar in two i32 pieces.
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Results.push_back(LowerBITREVERSE(SDValue(N, 0), Subtarget, DAG));
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return;
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}

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