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Reapply "[RISCV] Support RISCV Atomics ABI attributes (#84597)"
This patch adds support for the atomic_abi attribute, specifid in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version. This was previously reverted due to ld.bfd segfaulting w/ unknown riscv attributes. Attribute emission is now guarded by a backend flag `--riscv-abi-attributes`, which is off by default. Linker support in LLD for attribute merging is now in a standalone patch. Reviewers: kito-cheng, MaskRay, asb Reviewed By: MaskRay Pull Request: #90266
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9 files changed

+60
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lld/ELF/Arch/RISCV.cpp

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Original file line numberDiff line numberDiff line change
@@ -1134,6 +1134,10 @@ mergeAttributesSection(const SmallVector<InputSectionBase *, 0> &sections) {
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case RISCVAttrs::PRIV_SPEC_MINOR:
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case RISCVAttrs::PRIV_SPEC_REVISION:
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break;
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case RISCVAttrs::AttrType::ATOMIC_ABI:
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// TODO: Handle ATOMIC_ABI tag merging
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continue;
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}
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// Fallback for deprecated priv_spec* and other unknown attributes: retain

llvm/include/llvm/Support/RISCVAttributeParser.h

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@@ -24,6 +24,7 @@ class RISCVAttributeParser : public ELFAttributeParser {
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Error unalignedAccess(unsigned tag);
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Error stackAlign(unsigned tag);
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Error atomicAbi(unsigned tag);
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public:
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RISCVAttributeParser(ScopedPrinter *sw)

llvm/include/llvm/Support/RISCVAttributes.h

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@@ -32,6 +32,17 @@ enum AttrType : unsigned {
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PRIV_SPEC = 8,
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PRIV_SPEC_MINOR = 10,
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PRIV_SPEC_REVISION = 12,
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ATOMIC_ABI = 14,
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};
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enum class RISCVAtomicAbiTag : unsigned {
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// Values for Tag_RISCV_atomic_abi
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// Defined at
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// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version
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UNKNOWN = 0,
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A6C = 1,
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A6S = 2,
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A7 = 3,
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};
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enum { NOT_ALLOWED = 0, ALLOWED = 1 };

llvm/lib/Support/RISCVAttributeParser.cpp

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,18 @@ const RISCVAttributeParser::DisplayHandler
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{
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RISCVAttrs::UNALIGNED_ACCESS,
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&RISCVAttributeParser::unalignedAccess,
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}};
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},
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{
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RISCVAttrs::ATOMIC_ABI,
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&RISCVAttributeParser::atomicAbi,
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},
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};
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Error RISCVAttributeParser::atomicAbi(unsigned Tag) {
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uint64_t Value = de.getULEB128(cursor);
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printAttribute(Tag, Value, "Atomic ABI is " + utostr(Value));
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return Error::success();
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}
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Error RISCVAttributeParser::unalignedAccess(unsigned tag) {
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static const char *strings[] = {"No unaligned access", "Unaligned access"};

llvm/lib/Support/RISCVAttributes.cpp

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Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ static constexpr TagNameItem tagData[] = {
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{PRIV_SPEC, "Tag_priv_spec"},
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{PRIV_SPEC_MINOR, "Tag_priv_spec_minor"},
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{PRIV_SPEC_REVISION, "Tag_priv_spec_revision"},
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{ATOMIC_ABI, "Tag_atomic_abi"},
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};
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constexpr TagNameMap RISCVAttributeTags{tagData};

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

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Original file line numberDiff line numberDiff line change
@@ -14,12 +14,20 @@
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#include "RISCVBaseInfo.h"
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#include "RISCVMCTargetDesc.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/RISCVAttributes.h"
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#include "llvm/TargetParser/RISCVISAInfo.h"
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using namespace llvm;
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// This option controls wether or not we emit ELF attributes for ABI features,
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// like RISC-V atomics or X3 usage.
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static cl::opt<bool> RiscvAbiAttr(
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"riscv-abi-attributes",
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cl::desc("Enable emitting RISC-V ELF attributes for ABI features"),
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cl::Hidden);
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RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
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void RISCVTargetStreamer::finish() { finishAttributeSection(); }
@@ -75,6 +83,14 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
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auto &ISAInfo = *ParseResult;
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emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString());
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}
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if (RiscvAbiAttr && STI.hasFeature(RISCV::FeatureStdExtA)) {
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unsigned AtomicABITag =
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static_cast<unsigned>(STI.hasFeature(RISCV::FeatureTrailingSeqCstFence)
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? RISCVAttrs::RISCVAtomicAbiTag::A6S
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: RISCVAttrs::RISCVAtomicAbiTag::A6C);
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emitAttribute(RISCVAttrs::ATOMIC_ABI, AtomicABITag);
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}
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}
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// This part is for ascii assembly output

llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,8 @@
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; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
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; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s
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; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s
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; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A %s
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; RUN: llc -mtriple=riscv64 -mattr=+a --riscv-abi-attributes %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s
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; RUN: llc -mtriple=riscv64 -mattr=+a,+seq-cst-trailing-fence --riscv-abi-attributes %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s
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; RUN: llc -mtriple=riscv64 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV64B %s
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; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s
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; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s
@@ -565,3 +566,10 @@ define i32 @addi(i32 %a) {
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%1 = add i32 %a, 1
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ret i32 %1
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}
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define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind {
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%1 = load atomic i8, ptr %a seq_cst, align 1
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ret i8 %1
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; A6S: .attribute 14, 2
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; A6C: .attribute 14, 1
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}

llvm/test/MC/RISCV/attribute.s

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@@ -24,3 +24,6 @@
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.attribute priv_spec_revision, 0
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# CHECK: attribute 12, 0
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.attribute atomic_abi, 0
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# CHECK: attribute 14, 0

llvm/test/MC/RISCV/invalid-attribute.s

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@@ -33,3 +33,6 @@
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.attribute arch, 30
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# CHECK: [[@LINE-1]]:18: error: expected string constant
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.attribute atomic_abi, "16"
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# CHECK: [[@LINE-1]]:24: error: expected numeric constant

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