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[TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (#101751)
If the upper bits of the shr aren't demanded. This helps with cases where the outer srl was originally an sra and was converted to a srl by SimplifyDemandedBits before it had a chance to combine with the inner sra. This can occur when the inner sra was part of a sign_extend_inreg expansion. There are some regressions in ARM and Thumb2.
1 parent 294ed6a commit abc1acf

12 files changed

+74
-79
lines changed

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1958,6 +1958,22 @@ bool TargetLowering::SimplifyDemandedBits(
19581958
}
19591959
}
19601960

1961+
// If this is (srl (sra X, C1), ShAmt), see if we can combine this into a
1962+
// single sra. We can do this if the top bits are never demanded.
1963+
if (Op0.getOpcode() == ISD::SRA && Op0.hasOneUse()) {
1964+
if (!DemandedBits.intersects(APInt::getHighBitsSet(BitWidth, ShAmt))) {
1965+
if (std::optional<uint64_t> InnerSA =
1966+
TLO.DAG.getValidShiftAmount(Op0, DemandedElts, Depth + 2)) {
1967+
unsigned C1 = *InnerSA;
1968+
// Clamp the combined shift amount if it exceeds the bit width.
1969+
unsigned Combined = std::min(C1 + ShAmt, BitWidth - 1);
1970+
SDValue NewSA = TLO.DAG.getConstant(Combined, dl, ShiftVT);
1971+
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRA, dl, VT,
1972+
Op0.getOperand(0), NewSA));
1973+
}
1974+
}
1975+
}
1976+
19611977
APInt InDemandedMask = (DemandedBits << ShAmt);
19621978

19631979
// If the shift is exact, then it does demand the low bits (and knows that

‎llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,8 @@ define i1 @test_srem_even(i4 %X) nounwind {
4141
define i1 @test_srem_pow2_setne(i6 %X) nounwind {
4242
; CHECK-LABEL: test_srem_pow2_setne:
4343
; CHECK: // %bb.0:
44-
; CHECK-NEXT: sbfx w8, w0, #0, #6
45-
; CHECK-NEXT: ubfx w8, w8, #9, #2
44+
; CHECK-NEXT: sbfx w8, w0, #5, #1
45+
; CHECK-NEXT: and w8, w8, #0x3
4646
; CHECK-NEXT: add w8, w0, w8
4747
; CHECK-NEXT: and w8, w8, #0x3c
4848
; CHECK-NEXT: sub w8, w0, w8

‎llvm/test/CodeGen/AMDGPU/permute_i8.ll

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1049,15 +1049,14 @@ define hidden void @ashr_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
10491049
; GFX10-NEXT: global_load_dword v0, v[0:1], off
10501050
; GFX10-NEXT: s_waitcnt vmcnt(1)
10511051
; GFX10-NEXT: v_bfe_i32 v1, v9, 0, 8
1052-
; GFX10-NEXT: v_ashrrev_i32_e32 v3, 24, v9
10531052
; GFX10-NEXT: v_ashrrev_i32_sdwa v2, v2, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
1053+
; GFX10-NEXT: v_ashrrev_i32_e32 v3, 25, v9
10541054
; GFX10-NEXT: v_lshlrev_b16 v1, 7, v1
1055-
; GFX10-NEXT: v_lshrrev_b16 v3, 1, v3
1055+
; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
10561056
; GFX10-NEXT: s_waitcnt vmcnt(0)
10571057
; GFX10-NEXT: v_ashrrev_i16 v4, 10, v0
10581058
; GFX10-NEXT: v_perm_b32 v0, v9, v0, 0x4010707
10591059
; GFX10-NEXT: v_and_b32_e32 v1, 0xffffff00, v1
1060-
; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
10611060
; GFX10-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
10621061
; GFX10-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
10631062
; GFX10-NEXT: global_store_dword v[5:6], v1, off
@@ -1075,23 +1074,22 @@ define hidden void @ashr_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
10751074
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
10761075
; GFX9-NEXT: global_load_dword v4, v[0:1], off
10771076
; GFX9-NEXT: global_load_dword v9, v[2:3], off
1078-
; GFX9-NEXT: v_mov_b32_e32 v0, 26
1079-
; GFX9-NEXT: v_mov_b32_e32 v1, 1
1080-
; GFX9-NEXT: v_mov_b32_e32 v2, 7
1077+
; GFX9-NEXT: v_mov_b32_e32 v1, 7
10811078
; GFX9-NEXT: s_mov_b32 s4, 0x4010707
1079+
; GFX9-NEXT: v_mov_b32_e32 v0, 26
10821080
; GFX9-NEXT: s_waitcnt vmcnt(1)
1083-
; GFX9-NEXT: v_ashrrev_i32_sdwa v0, v0, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
1084-
; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v1, sext(v4) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
1085-
; GFX9-NEXT: v_lshlrev_b16_sdwa v2, v2, sext(v4) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1081+
; GFX9-NEXT: v_lshlrev_b16_sdwa v1, v1, sext(v4) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
10861082
; GFX9-NEXT: s_waitcnt vmcnt(0)
1087-
; GFX9-NEXT: v_perm_b32 v3, v4, v9, s4
1083+
; GFX9-NEXT: v_perm_b32 v2, v4, v9, s4
1084+
; GFX9-NEXT: v_ashrrev_i32_sdwa v0, v0, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
1085+
; GFX9-NEXT: v_ashrrev_i32_e32 v3, 25, v4
10881086
; GFX9-NEXT: v_ashrrev_i16_e32 v9, 10, v9
1089-
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1090-
; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff00, v2
1087+
; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff00, v1
1088+
; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
10911089
; GFX9-NEXT: v_or_b32_sdwa v1, v9, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
10921090
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
10931091
; GFX9-NEXT: global_store_dword v[5:6], v0, off
1094-
; GFX9-NEXT: global_store_dword v[7:8], v3, off
1092+
; GFX9-NEXT: global_store_dword v[7:8], v2, off
10951093
; GFX9-NEXT: s_waitcnt vmcnt(0)
10961094
; GFX9-NEXT: s_setpc_b64 s[30:31]
10971095
%tid = call i32 @llvm.amdgcn.workitem.id.x()

‎llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -43,8 +43,8 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
4343
; CHECK-LABEL: test_srem_pow2_setne:
4444
; CHECK: ; %bb.0:
4545
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
46-
; CHECK-NEXT: v_bfe_i32 v1, v0, 0, 6
47-
; CHECK-NEXT: v_bfe_u32 v1, v1, 9, 2
46+
; CHECK-NEXT: v_bfe_i32 v1, v0, 5, 1
47+
; CHECK-NEXT: v_and_b32_e32 v1, 3, v1
4848
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v0, v1
4949
; CHECK-NEXT: v_and_b32_e32 v1, 60, v1
5050
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1

‎llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -209,8 +209,7 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
209209
; ARM5: @ %bb.0:
210210
; ARM5-NEXT: lsl r1, r0, #26
211211
; ARM5-NEXT: mov r2, #3
212-
; ARM5-NEXT: asr r1, r1, #26
213-
; ARM5-NEXT: and r1, r2, r1, lsr #9
212+
; ARM5-NEXT: and r1, r2, r1, asr #31
214213
; ARM5-NEXT: add r1, r0, r1
215214
; ARM5-NEXT: and r1, r1, #60
216215
; ARM5-NEXT: sub r0, r0, r1
@@ -222,8 +221,7 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
222221
; ARM6: @ %bb.0:
223222
; ARM6-NEXT: lsl r1, r0, #26
224223
; ARM6-NEXT: mov r2, #3
225-
; ARM6-NEXT: asr r1, r1, #26
226-
; ARM6-NEXT: and r1, r2, r1, lsr #9
224+
; ARM6-NEXT: and r1, r2, r1, asr #31
227225
; ARM6-NEXT: add r1, r0, r1
228226
; ARM6-NEXT: and r1, r1, #60
229227
; ARM6-NEXT: sub r0, r0, r1
@@ -233,8 +231,9 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
233231
;
234232
; ARM7-LABEL: test_srem_pow2_setne:
235233
; ARM7: @ %bb.0:
236-
; ARM7-NEXT: sbfx r1, r0, #0, #6
237-
; ARM7-NEXT: ubfx r1, r1, #9, #2
234+
; ARM7-NEXT: lsl r1, r0, #26
235+
; ARM7-NEXT: mov r2, #3
236+
; ARM7-NEXT: and r1, r2, r1, asr #31
238237
; ARM7-NEXT: add r1, r0, r1
239238
; ARM7-NEXT: and r1, r1, #60
240239
; ARM7-NEXT: sub r0, r0, r1
@@ -244,8 +243,9 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
244243
;
245244
; ARM8-LABEL: test_srem_pow2_setne:
246245
; ARM8: @ %bb.0:
247-
; ARM8-NEXT: sbfx r1, r0, #0, #6
248-
; ARM8-NEXT: ubfx r1, r1, #9, #2
246+
; ARM8-NEXT: lsl r1, r0, #26
247+
; ARM8-NEXT: mov r2, #3
248+
; ARM8-NEXT: and r1, r2, r1, asr #31
249249
; ARM8-NEXT: add r1, r0, r1
250250
; ARM8-NEXT: and r1, r1, #60
251251
; ARM8-NEXT: sub r0, r0, r1
@@ -255,8 +255,9 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
255255
;
256256
; NEON7-LABEL: test_srem_pow2_setne:
257257
; NEON7: @ %bb.0:
258-
; NEON7-NEXT: sbfx r1, r0, #0, #6
259-
; NEON7-NEXT: ubfx r1, r1, #9, #2
258+
; NEON7-NEXT: lsl r1, r0, #26
259+
; NEON7-NEXT: mov r2, #3
260+
; NEON7-NEXT: and r1, r2, r1, asr #31
260261
; NEON7-NEXT: add r1, r0, r1
261262
; NEON7-NEXT: and r1, r1, #60
262263
; NEON7-NEXT: sub r0, r0, r1
@@ -266,8 +267,9 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
266267
;
267268
; NEON8-LABEL: test_srem_pow2_setne:
268269
; NEON8: @ %bb.0:
269-
; NEON8-NEXT: sbfx r1, r0, #0, #6
270-
; NEON8-NEXT: ubfx r1, r1, #9, #2
270+
; NEON8-NEXT: lsl r1, r0, #26
271+
; NEON8-NEXT: mov r2, #3
272+
; NEON8-NEXT: and r1, r2, r1, asr #31
271273
; NEON8-NEXT: add r1, r0, r1
272274
; NEON8-NEXT: and r1, r1, #60
273275
; NEON8-NEXT: sub r0, r0, r1

‎llvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -90,8 +90,7 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
9090
; MIPSEL-LABEL: test_srem_pow2_setne:
9191
; MIPSEL: # %bb.0:
9292
; MIPSEL-NEXT: sll $1, $4, 26
93-
; MIPSEL-NEXT: sra $1, $1, 26
94-
; MIPSEL-NEXT: srl $1, $1, 9
93+
; MIPSEL-NEXT: sra $1, $1, 31
9594
; MIPSEL-NEXT: andi $1, $1, 3
9695
; MIPSEL-NEXT: addu $1, $4, $1
9796
; MIPSEL-NEXT: andi $1, $1, 60
@@ -104,8 +103,7 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
104103
; MIPS64EL: # %bb.0:
105104
; MIPS64EL-NEXT: sll $1, $4, 0
106105
; MIPS64EL-NEXT: sll $2, $1, 26
107-
; MIPS64EL-NEXT: sra $2, $2, 26
108-
; MIPS64EL-NEXT: srl $2, $2, 9
106+
; MIPS64EL-NEXT: sra $2, $2, 31
109107
; MIPS64EL-NEXT: andi $2, $2, 3
110108
; MIPS64EL-NEXT: addu $2, $1, $2
111109
; MIPS64EL-NEXT: andi $2, $2, 60

‎llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -85,8 +85,8 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
8585
; PPC-LABEL: test_srem_pow2_setne:
8686
; PPC: # %bb.0:
8787
; PPC-NEXT: slwi 4, 3, 26
88-
; PPC-NEXT: srawi 4, 4, 26
89-
; PPC-NEXT: rlwinm 4, 4, 23, 30, 31
88+
; PPC-NEXT: srawi 4, 4, 31
89+
; PPC-NEXT: clrlwi 4, 4, 30
9090
; PPC-NEXT: add 4, 3, 4
9191
; PPC-NEXT: rlwinm 4, 4, 0, 26, 29
9292
; PPC-NEXT: sub 3, 3, 4
@@ -99,8 +99,8 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
9999
; PPC64LE-LABEL: test_srem_pow2_setne:
100100
; PPC64LE: # %bb.0:
101101
; PPC64LE-NEXT: slwi 4, 3, 26
102-
; PPC64LE-NEXT: srawi 4, 4, 26
103-
; PPC64LE-NEXT: rlwinm 4, 4, 23, 30, 31
102+
; PPC64LE-NEXT: srawi 4, 4, 31
103+
; PPC64LE-NEXT: clrlwi 4, 4, 30
104104
; PPC64LE-NEXT: add 4, 3, 4
105105
; PPC64LE-NEXT: rlwinm 4, 4, 0, 26, 29
106106
; PPC64LE-NEXT: sub 3, 3, 4

‎llvm/test/CodeGen/RISCV/div.ll

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1017,8 +1017,7 @@ define i8 @sdiv8_pow2(i8 %a) nounwind {
10171017
; RV32I-LABEL: sdiv8_pow2:
10181018
; RV32I: # %bb.0:
10191019
; RV32I-NEXT: slli a1, a0, 24
1020-
; RV32I-NEXT: srai a1, a1, 24
1021-
; RV32I-NEXT: slli a1, a1, 17
1020+
; RV32I-NEXT: srai a1, a1, 2
10221021
; RV32I-NEXT: srli a1, a1, 29
10231022
; RV32I-NEXT: add a0, a0, a1
10241023
; RV32I-NEXT: slli a0, a0, 24
@@ -1028,8 +1027,7 @@ define i8 @sdiv8_pow2(i8 %a) nounwind {
10281027
; RV32IM-LABEL: sdiv8_pow2:
10291028
; RV32IM: # %bb.0:
10301029
; RV32IM-NEXT: slli a1, a0, 24
1031-
; RV32IM-NEXT: srai a1, a1, 24
1032-
; RV32IM-NEXT: slli a1, a1, 17
1030+
; RV32IM-NEXT: srai a1, a1, 2
10331031
; RV32IM-NEXT: srli a1, a1, 29
10341032
; RV32IM-NEXT: add a0, a0, a1
10351033
; RV32IM-NEXT: slli a0, a0, 24
@@ -1039,8 +1037,7 @@ define i8 @sdiv8_pow2(i8 %a) nounwind {
10391037
; RV64I-LABEL: sdiv8_pow2:
10401038
; RV64I: # %bb.0:
10411039
; RV64I-NEXT: slli a1, a0, 56
1042-
; RV64I-NEXT: srai a1, a1, 56
1043-
; RV64I-NEXT: slli a1, a1, 49
1040+
; RV64I-NEXT: srai a1, a1, 2
10441041
; RV64I-NEXT: srli a1, a1, 61
10451042
; RV64I-NEXT: add a0, a0, a1
10461043
; RV64I-NEXT: slli a0, a0, 56
@@ -1050,8 +1047,7 @@ define i8 @sdiv8_pow2(i8 %a) nounwind {
10501047
; RV64IM-LABEL: sdiv8_pow2:
10511048
; RV64IM: # %bb.0:
10521049
; RV64IM-NEXT: slli a1, a0, 56
1053-
; RV64IM-NEXT: srai a1, a1, 56
1054-
; RV64IM-NEXT: slli a1, a1, 49
1050+
; RV64IM-NEXT: srai a1, a1, 2
10551051
; RV64IM-NEXT: srli a1, a1, 61
10561052
; RV64IM-NEXT: add a0, a0, a1
10571053
; RV64IM-NEXT: slli a0, a0, 56
@@ -1209,8 +1205,7 @@ define i16 @sdiv16_pow2(i16 %a) nounwind {
12091205
; RV32I-LABEL: sdiv16_pow2:
12101206
; RV32I: # %bb.0:
12111207
; RV32I-NEXT: slli a1, a0, 16
1212-
; RV32I-NEXT: srai a1, a1, 16
1213-
; RV32I-NEXT: slli a1, a1, 1
1208+
; RV32I-NEXT: srai a1, a1, 2
12141209
; RV32I-NEXT: srli a1, a1, 29
12151210
; RV32I-NEXT: add a0, a0, a1
12161211
; RV32I-NEXT: slli a0, a0, 16
@@ -1220,8 +1215,7 @@ define i16 @sdiv16_pow2(i16 %a) nounwind {
12201215
; RV32IM-LABEL: sdiv16_pow2:
12211216
; RV32IM: # %bb.0:
12221217
; RV32IM-NEXT: slli a1, a0, 16
1223-
; RV32IM-NEXT: srai a1, a1, 16
1224-
; RV32IM-NEXT: slli a1, a1, 1
1218+
; RV32IM-NEXT: srai a1, a1, 2
12251219
; RV32IM-NEXT: srli a1, a1, 29
12261220
; RV32IM-NEXT: add a0, a0, a1
12271221
; RV32IM-NEXT: slli a0, a0, 16
@@ -1231,8 +1225,7 @@ define i16 @sdiv16_pow2(i16 %a) nounwind {
12311225
; RV64I-LABEL: sdiv16_pow2:
12321226
; RV64I: # %bb.0:
12331227
; RV64I-NEXT: slli a1, a0, 48
1234-
; RV64I-NEXT: srai a1, a1, 48
1235-
; RV64I-NEXT: slli a1, a1, 33
1228+
; RV64I-NEXT: srai a1, a1, 2
12361229
; RV64I-NEXT: srli a1, a1, 61
12371230
; RV64I-NEXT: add a0, a0, a1
12381231
; RV64I-NEXT: slli a0, a0, 48
@@ -1242,8 +1235,7 @@ define i16 @sdiv16_pow2(i16 %a) nounwind {
12421235
; RV64IM-LABEL: sdiv16_pow2:
12431236
; RV64IM: # %bb.0:
12441237
; RV64IM-NEXT: slli a1, a0, 48
1245-
; RV64IM-NEXT: srai a1, a1, 48
1246-
; RV64IM-NEXT: slli a1, a1, 33
1238+
; RV64IM-NEXT: srai a1, a1, 2
12471239
; RV64IM-NEXT: srli a1, a1, 61
12481240
; RV64IM-NEXT: add a0, a0, a1
12491241
; RV64IM-NEXT: slli a0, a0, 48

‎llvm/test/CodeGen/RISCV/rv64zba.ll

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1555,16 +1555,14 @@ define zeroext i32 @sext_ashr_zext_i8(i8 %a) nounwind {
15551555
; RV64I-LABEL: sext_ashr_zext_i8:
15561556
; RV64I: # %bb.0:
15571557
; RV64I-NEXT: slli a0, a0, 56
1558-
; RV64I-NEXT: srai a0, a0, 56
1559-
; RV64I-NEXT: slli a0, a0, 23
1558+
; RV64I-NEXT: srai a0, a0, 31
15601559
; RV64I-NEXT: srli a0, a0, 32
15611560
; RV64I-NEXT: ret
15621561
;
15631562
; RV64ZBANOZBB-LABEL: sext_ashr_zext_i8:
15641563
; RV64ZBANOZBB: # %bb.0:
15651564
; RV64ZBANOZBB-NEXT: slli a0, a0, 56
1566-
; RV64ZBANOZBB-NEXT: srai a0, a0, 56
1567-
; RV64ZBANOZBB-NEXT: slli a0, a0, 23
1565+
; RV64ZBANOZBB-NEXT: srai a0, a0, 31
15681566
; RV64ZBANOZBB-NEXT: srli a0, a0, 32
15691567
; RV64ZBANOZBB-NEXT: ret
15701568
;
@@ -1674,16 +1672,14 @@ define zeroext i32 @sext_ashr_zext_i16(i16 %a) nounwind {
16741672
; RV64I-LABEL: sext_ashr_zext_i16:
16751673
; RV64I: # %bb.0:
16761674
; RV64I-NEXT: slli a0, a0, 48
1677-
; RV64I-NEXT: srai a0, a0, 48
1678-
; RV64I-NEXT: slli a0, a0, 23
1675+
; RV64I-NEXT: srai a0, a0, 25
16791676
; RV64I-NEXT: srli a0, a0, 32
16801677
; RV64I-NEXT: ret
16811678
;
16821679
; RV64ZBANOZBB-LABEL: sext_ashr_zext_i16:
16831680
; RV64ZBANOZBB: # %bb.0:
16841681
; RV64ZBANOZBB-NEXT: slli a0, a0, 48
1685-
; RV64ZBANOZBB-NEXT: srai a0, a0, 48
1686-
; RV64ZBANOZBB-NEXT: slli a0, a0, 23
1682+
; RV64ZBANOZBB-NEXT: srai a0, a0, 25
16871683
; RV64ZBANOZBB-NEXT: srli a0, a0, 32
16881684
; RV64ZBANOZBB-NEXT: ret
16891685
;

‎llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -222,8 +222,7 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
222222
; RV32-LABEL: test_srem_pow2_setne:
223223
; RV32: # %bb.0:
224224
; RV32-NEXT: slli a1, a0, 26
225-
; RV32-NEXT: srai a1, a1, 26
226-
; RV32-NEXT: slli a1, a1, 21
225+
; RV32-NEXT: srai a1, a1, 1
227226
; RV32-NEXT: srli a1, a1, 30
228227
; RV32-NEXT: add a1, a0, a1
229228
; RV32-NEXT: andi a1, a1, 60
@@ -235,8 +234,7 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
235234
; RV64-LABEL: test_srem_pow2_setne:
236235
; RV64: # %bb.0:
237236
; RV64-NEXT: slli a1, a0, 58
238-
; RV64-NEXT: srai a1, a1, 58
239-
; RV64-NEXT: slli a1, a1, 53
237+
; RV64-NEXT: srai a1, a1, 1
240238
; RV64-NEXT: srli a1, a1, 62
241239
; RV64-NEXT: add a1, a0, a1
242240
; RV64-NEXT: andi a1, a1, 60
@@ -248,8 +246,7 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
248246
; RV32M-LABEL: test_srem_pow2_setne:
249247
; RV32M: # %bb.0:
250248
; RV32M-NEXT: slli a1, a0, 26
251-
; RV32M-NEXT: srai a1, a1, 26
252-
; RV32M-NEXT: slli a1, a1, 21
249+
; RV32M-NEXT: srai a1, a1, 1
253250
; RV32M-NEXT: srli a1, a1, 30
254251
; RV32M-NEXT: add a1, a0, a1
255252
; RV32M-NEXT: andi a1, a1, 60
@@ -261,8 +258,7 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
261258
; RV64M-LABEL: test_srem_pow2_setne:
262259
; RV64M: # %bb.0:
263260
; RV64M-NEXT: slli a1, a0, 58
264-
; RV64M-NEXT: srai a1, a1, 58
265-
; RV64M-NEXT: slli a1, a1, 53
261+
; RV64M-NEXT: srai a1, a1, 1
266262
; RV64M-NEXT: srli a1, a1, 62
267263
; RV64M-NEXT: add a1, a0, a1
268264
; RV64M-NEXT: andi a1, a1, 60
@@ -274,8 +270,7 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
274270
; RV32MV-LABEL: test_srem_pow2_setne:
275271
; RV32MV: # %bb.0:
276272
; RV32MV-NEXT: slli a1, a0, 26
277-
; RV32MV-NEXT: srai a1, a1, 26
278-
; RV32MV-NEXT: slli a1, a1, 21
273+
; RV32MV-NEXT: srai a1, a1, 1
279274
; RV32MV-NEXT: srli a1, a1, 30
280275
; RV32MV-NEXT: add a1, a0, a1
281276
; RV32MV-NEXT: andi a1, a1, 60
@@ -287,8 +282,7 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
287282
; RV64MV-LABEL: test_srem_pow2_setne:
288283
; RV64MV: # %bb.0:
289284
; RV64MV-NEXT: slli a1, a0, 58
290-
; RV64MV-NEXT: srai a1, a1, 58
291-
; RV64MV-NEXT: slli a1, a1, 53
285+
; RV64MV-NEXT: srai a1, a1, 1
292286
; RV64MV-NEXT: srli a1, a1, 62
293287
; RV64MV-NEXT: add a1, a0, a1
294288
; RV64MV-NEXT: andi a1, a1, 60

‎llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,9 @@ define i1 @test_srem_even(i4 %X) nounwind {
4444
define i1 @test_srem_pow2_setne(i6 %X) nounwind {
4545
; CHECK-LABEL: test_srem_pow2_setne:
4646
; CHECK: @ %bb.0:
47-
; CHECK-NEXT: sbfx r1, r0, #0, #6
48-
; CHECK-NEXT: ubfx r1, r1, #9, #2
47+
; CHECK-NEXT: lsls r1, r0, #26
48+
; CHECK-NEXT: movs r2, #3
49+
; CHECK-NEXT: and.w r1, r2, r1, asr #31
4950
; CHECK-NEXT: add r1, r0
5051
; CHECK-NEXT: and r1, r1, #60
5152
; CHECK-NEXT: subs r0, r0, r1

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