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GlobalIsel code change, review comments
1 parent 2d06d3a commit a7ca93a

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7 files changed

+301
-207
lines changed

7 files changed

+301
-207
lines changed

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1204,15 +1204,18 @@ bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc(
12041204
auto WaveSize = B.buildConstant(LLT::scalar(32), ST.getWavefrontSizeLog2());
12051205
auto ScaledSize = B.buildShl(IntPtrTy, AllocSize, WaveSize);
12061206

1207-
auto SPCopy = B.buildCopy(PtrTy, SPReg);
1207+
auto OldSP = B.buildCopy(PtrTy, SPReg);
12081208
if (Alignment > TFI.getStackAlign()) {
1209-
auto PtrAdd = B.buildPtrAdd(PtrTy, SPCopy, ScaledSize);
1210-
B.buildMaskLowPtrBits(Dst, PtrAdd,
1209+
auto StackAlignMask = (Alignment.value() << ST.getWavefrontSizeLog2()) - 1;
1210+
auto Tmp1 = B.buildPtrAdd(PtrTy, OldSP,
1211+
B.buildConstant(LLT::scalar(32), StackAlignMask));
1212+
B.buildMaskLowPtrBits(Dst, Tmp1,
12111213
Log2(Alignment) + ST.getWavefrontSizeLog2());
12121214
} else {
1213-
B.buildPtrAdd(Dst, SPCopy, ScaledSize);
1215+
B.buildCopy(Dst, OldSP);
12141216
}
1215-
1217+
auto PtrAdd = B.buildPtrAdd(PtrTy, Dst, ScaledSize);
1218+
B.buildCopy(SPReg, PtrAdd);
12161219
MI.eraseFromParent();
12171220
return true;
12181221
}

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 16 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -4038,41 +4038,35 @@ SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(SDValue Op,
40384038
Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
40394039

40404040
SDValue Size = Tmp2.getOperand(1);
4041-
SDValue SPOld = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
4042-
Chain = SPOld.getValue(1);
4043-
MaybeAlign Alignment = cast<ConstantSDNode>(Tmp3)->getMaybeAlignValue();
4041+
SDValue BaseAddr = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
4042+
Align Alignment = cast<ConstantSDNode>(Tmp3)->getAlignValue();
4043+
40444044
const TargetFrameLowering *TFL = Subtarget->getFrameLowering();
40454045
assert(TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp &&
40464046
"Stack grows upwards for AMDGPU");
4047+
4048+
Chain = BaseAddr.getValue(1);
40474049
Align StackAlign = TFL->getStackAlign();
4048-
if (Alignment && *Alignment > StackAlign) {
4049-
SDValue ScaledAlignment = DAG.getSignedConstant(
4050-
(uint64_t)Alignment->value() << Subtarget->getWavefrontSizeLog2(), dl,
4051-
VT);
4052-
SDValue StackAlignMask = DAG.getNode(ISD::SUB, dl, VT, ScaledAlignment,
4053-
DAG.getConstant(1, dl, VT));
4054-
Tmp1 = DAG.getNode(ISD::ADD, dl, VT, SPOld, StackAlignMask);
4055-
Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1, ScaledAlignment);
4050+
if (Alignment > StackAlign) {
4051+
auto ScaledAlignment = (uint64_t)Alignment.value()
4052+
<< Subtarget->getWavefrontSizeLog2();
4053+
auto StackAlignMask = ScaledAlignment - 1;
4054+
auto TmpAddr = DAG.getNode(ISD::ADD, dl, VT, BaseAddr,
4055+
DAG.getConstant(StackAlignMask, dl, VT));
4056+
BaseAddr = DAG.getNode(ISD::AND, dl, VT, TmpAddr,
4057+
DAG.getConstant(ScaledAlignment, dl, VT));
40564058
}
40574059

40584060
SDValue ScaledSize = DAG.getNode(
40594061
ISD::SHL, dl, VT, Size,
40604062
DAG.getConstant(Subtarget->getWavefrontSizeLog2(), dl, MVT::i32));
40614063

4062-
Align StackAlign = TFL->getStackAlign();
4063-
Tmp1 = DAG.getNode(ISD::ADD, dl, VT, SPOld, ScaledSize); // Value
4064-
if (Alignment && *Alignment > StackAlign) {
4065-
Tmp1 = DAG.getNode(
4066-
ISD::AND, dl, VT, Tmp1,
4067-
DAG.getSignedConstant(-(uint64_t)Alignment->value()
4068-
<< Subtarget->getWavefrontSizeLog2(),
4069-
dl, VT));
4070-
}
4064+
auto NewSP = DAG.getNode(ISD::ADD, dl, VT, BaseAddr, ScaledSize); // Value
40714065

4072-
Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
4066+
Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP); // Output chain
40734067
Tmp2 = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), dl);
40744068

4075-
return DAG.getMergeValues({SPOld, Tmp2}, dl);
4069+
return DAG.getMergeValues({BaseAddr, Tmp2}, dl);
40764070
}
40774071

40784072
SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,

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