Skip to content

Commit a4fec16

Browse files
ilovepiilovepi
authored
Reapply "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)" (#90267)
With the tag merging in place, we can safely change the default for +seq-cst-trailing-fence to the default, according to the recommendation in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc This patch changes the default for the feature flag, and moves to more consistent naming with respect to existing features. This was reverted with #84597, because ld.bfd would segfault with unknown riscv attributes. Now that attributes emission is guarded with a backend flag, `--riscv-abi-attributes`, this should be safe to reland, since it won't introduce abi tags unless the user opts into them.
1 parent 526dbc1 commit a4fec16

File tree

7 files changed

+30
-25
lines changed

7 files changed

+30
-25
lines changed

‎llvm/docs/ReleaseNotes.rst

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -189,6 +189,11 @@ Changes to the RISC-V Backend
189189
* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
190190
* Added smcdeleg, ssccfg, smcsrind, and sscsrind extensions to -march.
191191
* ``-mcpu=syntacore-scr3-rv32`` and ``-mcpu=syntacore-scr3-rv64`` were added.
192+
* The default atomics mapping was changed to emit an additional trailing fence
193+
for sequentially consistent stores, offering compatibility with a future
194+
mapping using load-acquire and store-release instructions while remaining
195+
fully compatible with objects produced prior to this change. The mapping
196+
(ABI) used is recorded as an ELF attribute.
192197

193198
Changes to the WebAssembly Backend
194199
----------------------------------

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -85,10 +85,10 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
8585
}
8686

8787
if (RiscvAbiAttr && STI.hasFeature(RISCV::FeatureStdExtA)) {
88-
unsigned AtomicABITag =
89-
static_cast<unsigned>(STI.hasFeature(RISCV::FeatureTrailingSeqCstFence)
90-
? RISCVAttrs::RISCVAtomicAbiTag::A6S
91-
: RISCVAttrs::RISCVAtomicAbiTag::A6C);
88+
unsigned AtomicABITag = static_cast<unsigned>(
89+
STI.hasFeature(RISCV::FeatureNoTrailingSeqCstFence)
90+
? RISCVAttrs::RISCVAtomicAbiTag::A6C
91+
: RISCVAttrs::RISCVAtomicAbiTag::A6S);
9292
emitAttribute(RISCVAttrs::ATOMIC_ABI, AtomicABITag);
9393
}
9494
}

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1244,10 +1244,10 @@ foreach i = {1-31} in
12441244
def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
12451245
"true", "Enable save/restore.">;
12461246

1247-
def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence",
1248-
"EnableSeqCstTrailingFence",
1249-
"true",
1250-
"Enable trailing fence for seq-cst store.">;
1247+
def FeatureNoTrailingSeqCstFence : SubtargetFeature<"no-trailing-seq-cst-fence",
1248+
"EnableTrailingSeqCstFence",
1249+
"false",
1250+
"Disable trailing fence for seq-cst store.">;
12511251

12521252
def FeatureUnalignedScalarMem
12531253
: SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20882,7 +20882,7 @@ Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
2088220882

2088320883
if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord))
2088420884
return Builder.CreateFence(AtomicOrdering::Acquire);
20885-
if (Subtarget.enableSeqCstTrailingFence() && isa<StoreInst>(Inst) &&
20885+
if (Subtarget.enableTrailingSeqCstFence() && isa<StoreInst>(Inst) &&
2088620886
Ord == AtomicOrdering::SequentiallyConsistent)
2088720887
return Builder.CreateFence(AtomicOrdering::SequentiallyConsistent);
2088820888
return nullptr;

‎llvm/test/CodeGen/RISCV/atomic-load-store.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,26 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
33
; RUN: | FileCheck -check-prefix=RV32I %s
4-
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
4+
; RUN: llc -mtriple=riscv32 -mattr=+a,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
55
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO %s
6-
; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
6+
; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
77
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO %s
88
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
99
; RUN: | FileCheck -check-prefix=RV64I %s
10-
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
10+
; RUN: llc -mtriple=riscv64 -mattr=+a,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
1111
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO %s
12-
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
12+
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
1313
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO %s
1414

1515

16-
; RUN: llc -mtriple=riscv32 -mattr=+a,+seq-cst-trailing-fence -verify-machineinstrs < %s \
16+
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
1717
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO-TRAILING-FENCE %s
18-
; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso,+seq-cst-trailing-fence -verify-machineinstrs < %s \
18+
; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
1919
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO-TRAILING-FENCE %s
2020

21-
; RUN: llc -mtriple=riscv64 -mattr=+a,+seq-cst-trailing-fence -verify-machineinstrs < %s \
21+
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
2222
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO-TRAILING-FENCE %s
23-
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+seq-cst-trailing-fence -verify-machineinstrs < %s \
23+
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
2424
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO-TRAILING-FENCE %s
2525

2626

‎llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -135,8 +135,8 @@
135135
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
136136
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s
137137
; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s
138-
; RUN: llc -mtriple=riscv64 -mattr=+a --riscv-abi-attributes %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s
139-
; RUN: llc -mtriple=riscv64 -mattr=+a,+seq-cst-trailing-fence --riscv-abi-attributes %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s
138+
; RUN: llc -mtriple=riscv64 -mattr=+a,no-trailing-seq-cst-fence --riscv-abi-attributes %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s
139+
; RUN: llc -mtriple=riscv64 -mattr=+a --riscv-abi-attributes %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s
140140
; RUN: llc -mtriple=riscv64 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV64B %s
141141
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s
142142
; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s

‎llvm/test/CodeGen/RISCV/forced-atomics.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-NO-ATOMIC
2+
; RUN: llc -mtriple=riscv32 -mattr=+no-trailing-seq-cst-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-NO-ATOMIC
33
; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefixes=RV32,RV32-NO-ATOMIC
4-
; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC
5-
; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics,+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC-TRAILING
4+
; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics,+no-trailing-seq-cst-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC
5+
; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC-TRAILING
6+
; RUN: llc -mtriple=riscv64 -mattr=+no-trailing-seq-cst-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-NO-ATOMIC
67
; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefixes=RV64,RV64-NO-ATOMIC
7-
; RUN: llc -mtriple=riscv64 -mattr=+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-NO-ATOMIC
8-
; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC
9-
; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics,+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC-TRAILING
8+
; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics,+no-trailing-seq-cst-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC
9+
; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC-TRAILING
1010

1111
define i8 @load8(ptr %p) nounwind {
1212
; RV32-NO-ATOMIC-LABEL: load8:

0 commit comments

Comments
 (0)