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[CodeGen] Fix register pressure computation in MachinePipeliner (#87030)
`RegisterClassInfo::getRegPressureSetLimit` has been changed to return a smaller value than before so the limit may become negative in later calculations. As a workaround, change to use `TargetRegisterInfo::getRegPressureSetLimit`. Also improve tests.
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-166
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3 files changed

+180
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‎llvm/lib/CodeGen/MachinePipeliner.cpp

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@@ -1268,7 +1268,7 @@ class HighRegisterPressureDetector {
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// Calculate the upper limit of each pressure set
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void computePressureSetLimit(const RegisterClassInfo &RCI) {
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for (unsigned PSet = 0; PSet < PSetNum; PSet++)
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PressureSetLimit[PSet] = RCI.getRegPressureSetLimit(PSet);
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PressureSetLimit[PSet] = TRI->getRegPressureSetLimit(MF, PSet);
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// We assume fixed registers, such as stack pointer, are already in use.
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// Therefore subtracting the weight of the fixed registers from the limit of

‎llvm/test/CodeGen/AArch64/sms-regpress.mir

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# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-max-mii=40 -pipeliner-register-pressure -pipeliner-ii-search-range=30 -debug-only=pipeliner 2>&1 | FileCheck %s
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# Check that if the register pressure is too high, the schedule is rejected, II is incremented, and scheduling continues.
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# The specific value of II is not important.
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# CHECK: {{^ *}}Try to schedule with {{[0-9]+$}}
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# CHECK: {{^ *}}Rejected the schedule because of too high register pressure{{$}}
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# CHECK: {{^ *}}Try to schedule with {{[0-9]+$}}
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# CHECK: {{^ *}}Schedule Found? 1 (II={{[0-9]+}}){{$}}
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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define dso_local double @kernel(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, i32 noundef %n) local_unnamed_addr {
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entry:
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%0 = load double, ptr %a, align 8
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%arrayidx1 = getelementptr inbounds i8, ptr %a, i64 8
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%1 = load double, ptr %arrayidx1, align 8
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%cmp133 = icmp sgt i32 %n, 0
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br i1 %cmp133, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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%wide.trip.count = zext nneg i32 %n to i64
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br label %for.body
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for.cond.cleanup: ; preds = %for.body, %entry
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%res.0.lcssa = phi double [ 0.000000e+00, %entry ], [ %add54, %for.body ]
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ret double %res.0.lcssa
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for.body: ; preds = %for.body.preheader, %for.body
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%lsr.iv137 = phi i64 [ %wide.trip.count, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
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%lsr.iv = phi ptr [ %b, %for.body.preheader ], [ %scevgep, %for.body ]
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%res.0135 = phi double [ 0.000000e+00, %for.body.preheader ], [ %add54, %for.body ]
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%2 = load double, ptr %lsr.iv, align 8
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%3 = tail call double @llvm.fmuladd.f64(double %0, double %2, double %0)
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%4 = tail call double @llvm.fmuladd.f64(double %3, double %2, double %3)
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%5 = tail call double @llvm.fmuladd.f64(double %4, double %2, double %4)
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%6 = tail call double @llvm.fmuladd.f64(double %5, double %2, double %5)
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%7 = tail call double @llvm.fmuladd.f64(double %6, double %2, double %6)
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%8 = tail call double @llvm.fmuladd.f64(double %7, double %2, double %7)
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%9 = tail call double @llvm.fmuladd.f64(double %8, double %2, double %8)
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%10 = tail call double @llvm.fmuladd.f64(double %9, double %2, double %9)
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%11 = tail call double @llvm.fmuladd.f64(double %10, double %2, double %10)
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%12 = tail call double @llvm.fmuladd.f64(double %11, double %2, double %11)
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%13 = tail call double @llvm.fmuladd.f64(double %12, double %2, double %12)
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%14 = tail call double @llvm.fmuladd.f64(double %13, double %2, double %13)
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%15 = tail call double @llvm.fmuladd.f64(double %14, double %2, double %14)
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%16 = tail call double @llvm.fmuladd.f64(double %15, double %2, double %15)
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%17 = tail call double @llvm.fmuladd.f64(double %16, double %2, double %16)
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%18 = tail call double @llvm.fmuladd.f64(double %17, double %2, double %17)
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%add = fadd double %17, %18
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%19 = tail call double @llvm.fmuladd.f64(double %18, double %2, double %add)
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%add35 = fadd double %10, %19
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%20 = tail call double @llvm.fmuladd.f64(double %3, double %2, double %add35)
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%add38 = fadd double %11, %20
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%21 = tail call double @llvm.fmuladd.f64(double %4, double %2, double %add38)
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%add41 = fadd double %12, %21
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%22 = tail call double @llvm.fmuladd.f64(double %5, double %2, double %add41)
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%add44 = fadd double %14, %15
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%add45 = fadd double %13, %add44
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%add46 = fadd double %add45, %22
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%23 = tail call double @llvm.fmuladd.f64(double %6, double %2, double %add46)
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%mul = fmul double %2, %7
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%mul51 = fmul double %1, %mul
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%24 = tail call double @llvm.fmuladd.f64(double %mul51, double %9, double %23)
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%25 = tail call double @llvm.fmuladd.f64(double %8, double %1, double %24)
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%add54 = fadd double %res.0135, %25
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%scevgep = getelementptr i8, ptr %lsr.iv, i64 8
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%lsr.iv.next = add nsw i64 %lsr.iv137, -1
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%exitcond.not = icmp eq i64 %lsr.iv.next, 0
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}
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declare double @llvm.fmuladd.f64(double, double, double)
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...
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---
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name: kernel
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0', virtual-reg: '%10' }
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- { reg: '$x1', virtual-reg: '%11' }
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- { reg: '$w2', virtual-reg: '%12' }
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body: |
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bb.0.entry:
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successors: %bb.1, %bb.4
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liveins: $x0, $x1, $w2
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%12:gpr32common = COPY $w2
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%11:gpr64 = COPY $x1
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%10:gpr64common = COPY $x0
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dead $wzr = SUBSWri %12, 1, 0, implicit-def $nzcv
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Bcc 10, %bb.1, implicit $nzcv
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bb.4:
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%13:fpr64 = FMOVD0
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B %bb.2
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bb.1.for.body.preheader:
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%0:fpr64 = LDRDui %10, 0 :: (load (s64) from %ir.a)
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%1:fpr64 = LDRDui %10, 1 :: (load (s64) from %ir.arrayidx1)
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%16:gpr32 = ORRWrs $wzr, %12, 0
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%2:gpr64all = SUBREG_TO_REG 0, killed %16, %subreg.sub_32
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%15:fpr64 = FMOVD0
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B %bb.3
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bb.2.for.cond.cleanup:
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%3:fpr64 = PHI %13, %bb.4, %7, %bb.3
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$d0 = COPY %3
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RET_ReallyLR implicit $d0
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bb.3.for.body:
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successors: %bb.2, %bb.3
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%4:gpr64sp = PHI %2, %bb.1, %9, %bb.3
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%5:gpr64sp = PHI %11, %bb.1, %8, %bb.3
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%6:fpr64 = PHI %15, %bb.1, %7, %bb.3
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early-clobber %17:gpr64sp, %18:fpr64 = LDRDpost %5, 8 :: (load (s64) from %ir.lsr.iv)
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%19:fpr64 = nofpexcept FMADDDrrr %0, %18, %0, implicit $fpcr
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%20:fpr64 = nofpexcept FMADDDrrr %19, %18, %19, implicit $fpcr
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%21:fpr64 = nofpexcept FMADDDrrr %20, %18, %20, implicit $fpcr
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%22:fpr64 = nofpexcept FMADDDrrr %21, %18, %21, implicit $fpcr
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%23:fpr64 = nofpexcept FMADDDrrr %22, %18, %22, implicit $fpcr
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%24:fpr64 = nofpexcept FMADDDrrr %23, %18, %23, implicit $fpcr
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%25:fpr64 = nofpexcept FMADDDrrr %24, %18, %24, implicit $fpcr
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%26:fpr64 = nofpexcept FMADDDrrr %25, %18, %25, implicit $fpcr
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%27:fpr64 = nofpexcept FMADDDrrr %26, %18, %26, implicit $fpcr
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%28:fpr64 = nofpexcept FMADDDrrr %27, %18, %27, implicit $fpcr
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%29:fpr64 = nofpexcept FMADDDrrr %28, %18, %28, implicit $fpcr
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%30:fpr64 = nofpexcept FMADDDrrr %29, %18, %29, implicit $fpcr
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%31:fpr64 = nofpexcept FMADDDrrr %30, %18, %30, implicit $fpcr
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%32:fpr64 = nofpexcept FMADDDrrr %31, %18, %31, implicit $fpcr
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%33:fpr64 = nofpexcept FMADDDrrr %32, %18, %32, implicit $fpcr
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%34:fpr64 = nofpexcept FMADDDrrr %33, %18, %33, implicit $fpcr
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%35:fpr64 = nofpexcept FADDDrr %33, %34, implicit $fpcr
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%36:fpr64 = nofpexcept FMADDDrrr %34, %18, killed %35, implicit $fpcr
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%37:fpr64 = nofpexcept FADDDrr %26, killed %36, implicit $fpcr
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%38:fpr64 = nofpexcept FMADDDrrr %19, %18, killed %37, implicit $fpcr
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%39:fpr64 = nofpexcept FADDDrr %27, killed %38, implicit $fpcr
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%40:fpr64 = nofpexcept FMADDDrrr %20, %18, killed %39, implicit $fpcr
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%41:fpr64 = nofpexcept FADDDrr %28, killed %40, implicit $fpcr
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%42:fpr64 = nofpexcept FMADDDrrr %21, %18, killed %41, implicit $fpcr
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%43:fpr64 = nofpexcept FADDDrr %30, %31, implicit $fpcr
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%44:fpr64 = nofpexcept FADDDrr %29, killed %43, implicit $fpcr
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%45:fpr64 = nofpexcept FADDDrr killed %44, killed %42, implicit $fpcr
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%46:fpr64 = nofpexcept FMADDDrrr %22, %18, killed %45, implicit $fpcr
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%47:fpr64 = nofpexcept FMULDrr %18, %23, implicit $fpcr
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%48:fpr64 = nofpexcept FMULDrr %1, killed %47, implicit $fpcr
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%49:fpr64 = nofpexcept FMADDDrrr killed %48, %25, killed %46, implicit $fpcr
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%50:fpr64 = nofpexcept FMADDDrrr %24, %1, killed %49, implicit $fpcr
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%7:fpr64 = nofpexcept FADDDrr %6, killed %50, implicit $fpcr
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%8:gpr64all = COPY %17
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%51:gpr64 = nsw SUBSXri %4, 1, 0, implicit-def $nzcv
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%9:gpr64all = COPY %51
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Bcc 0, %bb.2, implicit $nzcv
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B %bb.3
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...

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