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| 1 | +// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s |
| 2 | + |
| 3 | +// This file tests that a synthesized sub-regclass can inherit properties, e.g., |
| 4 | +// tsflags in this case, from the correct super-regclass. |
| 5 | + |
| 6 | +include "llvm/Target/Target.td" |
| 7 | + |
| 8 | +class MyReg<string n, list<Register> subregs = []> |
| 9 | + : Register<n> { |
| 10 | + let Namespace = "Test"; |
| 11 | + let SubRegs = subregs; |
| 12 | + let CoveredBySubRegs = 1; |
| 13 | +} |
| 14 | + |
| 15 | +class MyClass<int align, list<ValueType> types, dag registers> |
| 16 | + : RegisterClass<"Test", types, align, registers> { |
| 17 | + field bit isA = 0; |
| 18 | + field bit isB = 0; |
| 19 | + let TSFlags{0} = isA; |
| 20 | + let TSFlags{1} = isB; |
| 21 | +} |
| 22 | + |
| 23 | +def sub0 : SubRegIndex<32, 0>; |
| 24 | +def sub1 : SubRegIndex<32, 32>; |
| 25 | +def sub2 : SubRegIndex<32, 64>; |
| 26 | + |
| 27 | +foreach Num=0-7 in { |
| 28 | + def A#Num : MyReg<"a"#Num>; |
| 29 | +} |
| 30 | + |
| 31 | +foreach Num=0-3 in { |
| 32 | + def B#Num : MyReg<"b"#Num>; |
| 33 | +} |
| 34 | + |
| 35 | +class AClass<int align, list<ValueType> types, dag registers> |
| 36 | + : MyClass<align, types, registers> { |
| 37 | + let isA = 1; |
| 38 | +} |
| 39 | + |
| 40 | +class BClass<int align, list<ValueType> types, dag registers> |
| 41 | + : MyClass<align, types, registers> { |
| 42 | + let isB = 1; |
| 43 | +} |
| 44 | + |
| 45 | +def APair : RegisterTuples<[sub0, sub1], |
| 46 | + [(add A0, A2, A4, A6), (add A1, A3, A5, A7)]>; |
| 47 | +def BPair : RegisterTuples<[sub0, sub1], |
| 48 | + [(add B0, B2), (add B1, B3)]>; |
| 49 | +def ARC2 : AClass<32, [untyped], (add APair)>; |
| 50 | +def BRC2 : BClass<32, [untyped], (add BPair)>; |
| 51 | +def ABRC2 : MyClass<32, [untyped], (add ARC2, BRC2)> { |
| 52 | + let isAllocatable = 0; |
| 53 | +} |
| 54 | + |
| 55 | +def ATuple : RegisterTuples<[sub0, sub1, sub2], |
| 56 | + [(add A0, A1, A2, A3, A4, A5), |
| 57 | + (add A1, A2, A3, A4, A5, A6), |
| 58 | + (add A2, A3, A4, A5, A6, A7)]>; |
| 59 | + |
| 60 | +def BTuple : RegisterTuples<[sub0, sub1, sub2], |
| 61 | + [(add B0, B1), (add B1, B2), (add B2, B3)]>; |
| 62 | + |
| 63 | +def ARC3 : AClass<32, [untyped], (add ATuple)>; |
| 64 | +def BRC3 : BClass<32, [untyped], (add BTuple)>; |
| 65 | +def ABRC3 : MyClass<32, [untyped], (add ARC3, BRC3)> { |
| 66 | + let isAllocatable = 0; |
| 67 | +} |
| 68 | + |
| 69 | +def TestTarget : Target; |
| 70 | + |
| 71 | +// CHECK: static unsigned const ARC3_with_sub0_sub1Superclasses[] = { |
| 72 | +// CHECK-NEXT: Test::ABRC3RegClassID, |
| 73 | +// CHECK-NEXT: Test::ARC3RegClassID, |
| 74 | +// CHECK-NEXT: Test::ABRC3_with_sub0_sub1RegClassID, |
| 75 | +// CHECK-NEXT: }; |
| 76 | + |
| 77 | +// CHECK: static unsigned const ARC3_with_sub1_sub2Superclasses[] = { |
| 78 | +// CHECK-NEXT: Test::ABRC3RegClassID, |
| 79 | +// CHECK-NEXT: Test::ARC3RegClassID, |
| 80 | +// CHECK-NEXT: Test::ABRC3_with_sub1_sub2RegClassID, |
| 81 | +// CHECK-NEXT: }; |
| 82 | + |
| 83 | +// CHECK: extern const TargetRegisterClass ARC3_with_sub0_sub1RegClass = { |
| 84 | +// CHECK: 0x01, /* TSFlags */ |
| 85 | + |
| 86 | +// CHECK: extern const TargetRegisterClass ARC3_with_sub1_sub2RegClass = { |
| 87 | +// CHECK: 0x01, /* TSFlags */ |
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