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[X86][MOVRS] Support MOVRS (#116181)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
1 parent 251958f commit 9f06129

22 files changed

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‎.icslock

Whitespace-only changes.

‎clang/docs/ReleaseNotes.rst

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Original file line numberDiff line numberDiff line change
@@ -752,6 +752,7 @@ X86 Support
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- Support ISA of ``AMX-MOVRS``.
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- Support ISA of ``AMX-AVX512``.
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- Support ISA of ``AMX-TF32``.
755+
- Support ISA of ``MOVRS``.
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Arm and AArch64 Support
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^^^^^^^^^^^^^^^^^^^^^^^

‎clang/include/clang/Basic/BuiltinsX86.def

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@@ -660,6 +660,9 @@ TARGET_BUILTIN(__builtin_ia32_vpdpbuud256, "V8iV8iV8iV8i", "ncV:256:", "avxvnnii
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TARGET_BUILTIN(__builtin_ia32_vpdpbuuds128, "V4iV4iV4iV4i", "ncV:128:", "avxvnniint8|avx10.2-256")
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TARGET_BUILTIN(__builtin_ia32_vpdpbuuds256, "V8iV8iV8iV8i", "ncV:256:", "avxvnniint8|avx10.2-256")
662662

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// MOVRS
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TARGET_BUILTIN(__builtin_ia32_prefetchrs, "vvC*", "nc", "movrs")
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663666
TARGET_BUILTIN(__builtin_ia32_gather3div2df, "V2dV2dvC*V2OiUcIi", "nV:128:", "avx512vl")
664667
TARGET_BUILTIN(__builtin_ia32_gather3div2di, "V2OiV2OivC*V2OiUcIi", "nV:128:", "avx512vl")
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TARGET_BUILTIN(__builtin_ia32_gather3div4df, "V4dV4dvC*V4OiUcIi", "nV:256:", "avx512vl")

‎clang/include/clang/Basic/BuiltinsX86_64.def

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Original file line numberDiff line numberDiff line change
@@ -228,6 +228,12 @@ TARGET_BUILTIN(__builtin_ia32_aand64, "vv*SOi", "n", "raoint")
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TARGET_BUILTIN(__builtin_ia32_aor64, "vv*SOi", "n", "raoint")
229229
TARGET_BUILTIN(__builtin_ia32_axor64, "vv*SOi", "n", "raoint")
230230

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// MOVRS
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TARGET_BUILTIN(__builtin_ia32_movrsqi, "ScvC*", "n", "movrs")
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TARGET_BUILTIN(__builtin_ia32_movrshi, "SsvC*", "n", "movrs")
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TARGET_BUILTIN(__builtin_ia32_movrssi, "SivC*", "n", "movrs")
235+
TARGET_BUILTIN(__builtin_ia32_movrsdi, "SLLivC*", "n", "movrs")
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// MOVRS and AVX10.2
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TARGET_BUILTIN(__builtin_ia32_vmovrsb128, "V16cV16cC*", "nV:128:", "movrs,avx10.2-256")
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TARGET_BUILTIN(__builtin_ia32_vmovrsb256, "V32cV32cC*", "nV:256:", "movrs,avx10.2-256")

‎clang/lib/Headers/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -233,6 +233,7 @@ set(x86_files
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movdirintrin.h
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movrs_avx10_2_512intrin.h
235235
movrs_avx10_2intrin.h
236+
movrsintrin.h
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mwaitxintrin.h
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nmmintrin.h
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pconfigintrin.h

‎clang/lib/Headers/immintrin.h

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Original file line numberDiff line numberDiff line change
@@ -605,6 +605,10 @@ _storebe_i64(void * __P, long long __D) {
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#include <movdirintrin.h>
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#endif
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#if !defined(__SCE__) || __has_feature(modules) || defined(__MOVRS__)
609+
#include <movrsintrin.h>
610+
#endif
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#if !defined(__SCE__) || __has_feature(modules) || \
609613
(defined(__AVX10_2__) && defined(__MOVRS__))
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#include <movrs_avx10_2intrin.h>

‎clang/lib/Headers/movrsintrin.h

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@@ -0,0 +1,59 @@
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/*===---------------- movrsintrin.h - MOVRS intrinsics ----------------------===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
*
7+
*===----------------------------------------------------------------------===*/
8+
9+
#ifndef __IMMINTRIN_H
10+
#error "Never use <movrsintrin.h> directly; include <immintrin.h> instead."
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#endif // __IMMINTRIN_H
12+
13+
#ifndef __MOVRSINTRIN_H
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#define __MOVRSINTRIN_H
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#define __DEFAULT_FN_ATTRS \
17+
__attribute__((__always_inline__, __nodebug__, __target__("movrs")))
18+
19+
#ifdef __x86_64__
20+
static __inline__ char __DEFAULT_FN_ATTRS _movrs_i8(const void *__A) {
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return (char)__builtin_ia32_movrsqi((const void *)__A);
22+
}
23+
24+
static __inline__ short __DEFAULT_FN_ATTRS _movrs_i16(const void *__A) {
25+
return (short)__builtin_ia32_movrshi((const void *)__A);
26+
}
27+
28+
static __inline__ int __DEFAULT_FN_ATTRS _movrs_i32(const void *__A) {
29+
return (int)__builtin_ia32_movrssi((const void *)__A);
30+
}
31+
32+
static __inline__ long long __DEFAULT_FN_ATTRS _movrs_i64(const void *__A) {
33+
return (long long)__builtin_ia32_movrsdi((const void *)__A);
34+
}
35+
#endif // __x86_64__
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// Loads a memory sequence containing the specified memory address into
38+
/// the L3 data cache. Data will be shared (read/written) to by requesting
39+
/// core and other cores.
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///
41+
/// Note that the effect of this intrinsic is dependent on the processor
42+
/// implementation.
43+
///
44+
/// \headerfile <x86intrin.h>
45+
///
46+
/// This intrinsic corresponds to the \c PREFETCHRS instruction.
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///
48+
/// \param __P
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/// A pointer specifying the memory address to be prefetched.
50+
static __inline__ void __DEFAULT_FN_ATTRS
51+
_m_prefetchrs(volatile const void *__P) {
52+
#pragma clang diagnostic push
53+
#pragma clang diagnostic ignored "-Wcast-qual"
54+
__builtin_ia32_prefetchrs((const void *)__P);
55+
#pragma clang diagnostic pop
56+
}
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58+
#undef __DEFAULT_FN_ATTRS
59+
#endif // __MOVRSINTRIN_H

‎clang/test/CodeGen/X86/movrs-builtins.c

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@@ -0,0 +1,35 @@
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// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64-unknown-unknown -target-feature +movrs \
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// RUN: -emit-llvm -o - -Wall -Werror -pedantic -Wno-gnu-statement-expression | FileCheck %s
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#include <immintrin.h>
5+
#include <stddef.h>
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7+
char test_movrs_si8(const char * __A) {
8+
// CHECK-LABEL: @test_movrs_si8(
9+
// CHECK: call i8 @llvm.x86.movrsqi(
10+
return _movrs_i8(__A);
11+
}
12+
13+
short test_movrs_si16(const short * __A) {
14+
// CHECK-LABEL: @test_movrs_si16(
15+
// CHECK: call i16 @llvm.x86.movrshi(
16+
return _movrs_i16(__A);
17+
}
18+
19+
int test_movrs_si32(const int * __A) {
20+
// CHECK-LABEL: @test_movrs_si32(
21+
// CHECK: call i32 @llvm.x86.movrssi(
22+
return _movrs_i32(__A);
23+
}
24+
25+
long long test_movrs_si64(const long long * __A) {
26+
// CHECK-LABEL: @test_movrs_si64(
27+
// CHECK: call i64 @llvm.x86.movrsdi(
28+
return _movrs_i64(__A);
29+
}
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31+
void test_m_prefetch_rs(void *p) {
32+
_m_prefetchrs(p);
33+
// CHECK-LABEL: define{{.*}} void @test_m_prefetch_rs
34+
// CHECK: call void @llvm.x86.prefetchrs({{.*}})
35+
}

‎llvm/include/llvm/IR/IntrinsicsX86.td

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@@ -7877,3 +7877,20 @@ def int_x86_avx10_vmovrsw512 : ClangBuiltin<"__builtin_ia32_vmovrsw512">,
78777877
DefaultAttrsIntrinsic<[llvm_v32i16_ty], [llvm_ptr_ty],
78787878
[IntrReadMem]>;
78797879
}
7880+
7881+
let TargetPrefix = "x86" in {
7882+
def int_x86_movrsqi : ClangBuiltin<"__builtin_ia32_movrsqi">,
7883+
Intrinsic<[llvm_i8_ty], [llvm_ptr_ty],
7884+
[IntrReadMem]>;
7885+
def int_x86_movrshi : ClangBuiltin<"__builtin_ia32_movrshi">,
7886+
Intrinsic<[llvm_i16_ty], [llvm_ptr_ty],
7887+
[IntrReadMem]>;
7888+
def int_x86_movrssi : ClangBuiltin<"__builtin_ia32_movrssi">,
7889+
Intrinsic<[llvm_i32_ty], [llvm_ptr_ty],
7890+
[IntrReadMem]>;
7891+
def int_x86_movrsdi : ClangBuiltin<"__builtin_ia32_movrsdi">,
7892+
Intrinsic<[llvm_i64_ty], [llvm_ptr_ty],
7893+
[IntrReadMem]>;
7894+
def int_x86_prefetchrs : ClangBuiltin<"__builtin_ia32_prefetchrs">,
7895+
Intrinsic<[], [llvm_ptr_ty], []>;
7896+
}

‎llvm/lib/Target/X86/X86DiscriminateMemOps.cpp

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@@ -71,7 +71,8 @@ class X86DiscriminateMemOps : public MachineFunctionPass {
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bool IsPrefetchOpcode(unsigned Opcode) {
7272
return Opcode == X86::PREFETCHNTA || Opcode == X86::PREFETCHT0 ||
7373
Opcode == X86::PREFETCHT1 || Opcode == X86::PREFETCHT2 ||
74-
Opcode == X86::PREFETCHIT0 || Opcode == X86::PREFETCHIT1;
74+
Opcode == X86::PREFETCHIT0 || Opcode == X86::PREFETCHIT1 ||
75+
Opcode == X86::PREFETCHRST2;
7576
}
7677
} // end anonymous namespace
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‎llvm/lib/Target/X86/X86InstrMisc.td

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@@ -1727,3 +1727,27 @@ def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src",
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let Predicates = [HasCLDEMOTE], SchedRW = [WriteLoad] in
17281728
def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src",
17291729
[(int_x86_cldemote addr:$src)]>, TB;
1730+
1731+
//===----------------------------------------------------------------------===//
1732+
// MOVRS Instructions
1733+
//
1734+
1735+
let SchedRW = [WriteLoad] in {
1736+
let Predicates = [HasMOVRS, NoEGPR] in {
1737+
def MOVRS8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1738+
"movrs{b}\t{$src, $dst|$dst, $src}",
1739+
[(set GR8:$dst, (int_x86_movrsqi addr:$src))]>, T8;
1740+
def MOVRS16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1741+
"movrs{w}\t{$src, $dst|$dst, $src}",
1742+
[(set GR16:$dst, (int_x86_movrshi addr:$src))]>, OpSize16, T8;
1743+
def MOVRS32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1744+
"movrs{l}\t{$src, $dst|$dst, $src}",
1745+
[(set GR32:$dst, (int_x86_movrssi addr:$src))]>, OpSize32, T8;
1746+
def MOVRS64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1747+
"movrs{q}\t{$src, $dst|$dst, $src}",
1748+
[(set GR64:$dst, (int_x86_movrsdi addr:$src))]>, T8;
1749+
def PREFETCHRST2 : I<0x18, MRM4m, (outs), (ins i8mem:$src),
1750+
"prefetchrst2\t$src",
1751+
[(int_x86_prefetchrs addr:$src)]>, TB;
1752+
}
1753+
}

‎llvm/test/CodeGen/X86/movrs-builtins.ll

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@@ -0,0 +1,46 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+movrs | FileCheck %s
3+
4+
define i8 @test_movrs_si8(ptr %__A) {
5+
; CHECK-LABEL: test_movrs_si8:
6+
; CHECK: # %bb.0: # %entry
7+
; CHECK-NEXT: movrsb (%rdi), %al # encoding: [0x0f,0x38,0x8a,0x07]
8+
; CHECK-NEXT: retq # encoding: [0xc3]
9+
entry:
10+
%0 = call i8 @llvm.x86.movrsqi(ptr %__A)
11+
ret i8 %0
12+
}
13+
declare i8 @llvm.x86.movrsqi(ptr)
14+
15+
define i16 @test_movrs_si16(ptr %__A) {
16+
; CHECK-LABEL: test_movrs_si16:
17+
; CHECK: # %bb.0: # %entry
18+
; CHECK-NEXT: movrsw (%rdi), %ax # encoding: [0x66,0x0f,0x38,0x8b,0x07]
19+
; CHECK-NEXT: retq # encoding: [0xc3]
20+
entry:
21+
%0 = call i16 @llvm.x86.movrshi(ptr %__A)
22+
ret i16 %0
23+
}
24+
declare i16 @llvm.x86.movrshi(ptr)
25+
26+
define i32 @test_movrs_si32(ptr %__A) {
27+
; CHECK-LABEL: test_movrs_si32:
28+
; CHECK: # %bb.0: # %entry
29+
; CHECK-NEXT: movrsl (%rdi), %eax # encoding: [0x0f,0x38,0x8b,0x07]
30+
; CHECK-NEXT: retq # encoding: [0xc3]
31+
entry:
32+
%0 = call i32 @llvm.x86.movrssi(ptr %__A)
33+
ret i32 %0
34+
}
35+
declare i32 @llvm.x86.movrssi(ptr)
36+
37+
define i64 @test_movrs_si64(ptr %__A) {
38+
; CHECK-LABEL: test_movrs_si64:
39+
; CHECK: # %bb.0: # %entry
40+
; CHECK-NEXT: movrsq (%rdi), %rax # encoding: [0x48,0x0f,0x38,0x8b,0x07]
41+
; CHECK-NEXT: retq # encoding: [0xc3]
42+
entry:
43+
%0 = call i64 @llvm.x86.movrsdi(ptr %__A)
44+
ret i64 %0
45+
}
46+
declare i64 @llvm.x86.movrsdi(ptr)

‎llvm/test/CodeGen/X86/movrs-prefetch-builtins.ll

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@@ -0,0 +1,14 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prfchw,+movrs | FileCheck %s
3+
; RUN: llc < %s -mtriple=i686-- -mattr=-sse,+prfchw,+movrs | FileCheck %s
4+
5+
define void @t(ptr %ptr) nounwind {
6+
; CHECK-LABEL: t:
7+
; CHECK: # %bb.0: # %entry
8+
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
9+
; CHECK-NEXT: prefetchrst2 (%eax)
10+
; CHECK-NEXT: retl
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entry:
12+
tail call void @llvm.x86.prefetchrs( ptr %ptr )
13+
ret void
14+
}

‎llvm/test/MC/Disassembler/X86/movrs.txt

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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: movrsb 268435456(%rbp,%r14,8), %bl
5+
# INTEL: movrs bl, byte ptr [rbp + 8*r14 + 268435456]
6+
0x42,0x0f,0x38,0x8a,0x9c,0xf5,0x00,0x00,0x00,0x10
7+
8+
# ATT: movrsb 291(%r8,%rax,4), %bl
9+
# INTEL: movrs bl, byte ptr [r8 + 4*rax + 291]
10+
0x41,0x0f,0x38,0x8a,0x9c,0x80,0x23,0x01,0x00,0x00
11+
12+
# ATT: movrsb (%rip), %bl
13+
# INTEL: movrs bl, byte ptr [rip]
14+
0x0f,0x38,0x8a,0x1d,0x00,0x00,0x00,0x00
15+
16+
# ATT: movrsb -32(,%rbp,2), %bl
17+
# INTEL: movrs bl, byte ptr [2*rbp - 32]
18+
0x0f,0x38,0x8a,0x1c,0x6d,0xe0,0xff,0xff,0xff
19+
20+
# ATT: movrsb 127(%rcx), %bl
21+
# INTEL: movrs bl, byte ptr [rcx + 127]
22+
0x0f,0x38,0x8a,0x59,0x7f
23+
24+
# ATT: movrsb -128(%rdx), %bl
25+
# INTEL: movrs bl, byte ptr [rdx - 128]
26+
0x0f,0x38,0x8a,0x5a,0x80
27+
28+
# ATT: movrsw 268435456(%rbp,%r14,8), %bx
29+
# INTEL: movrs bx, word ptr [rbp + 8*r14 + 268435456]
30+
0x66,0x42,0x0f,0x38,0x8b,0x9c,0xf5,0x00,0x00,0x00,0x10
31+
32+
# ATT: movrsw 291(%r8,%rax,4), %bx
33+
# INTEL: movrs bx, word ptr [r8 + 4*rax + 291]
34+
0x66,0x41,0x0f,0x38,0x8b,0x9c,0x80,0x23,0x01,0x00,0x00
35+
36+
# ATT: movrsw (%rip), %bx
37+
# INTEL: movrs bx, word ptr [rip]
38+
0x66,0x0f,0x38,0x8b,0x1d,0x00,0x00,0x00,0x00
39+
40+
# ATT: movrsw -32(,%rbp,2), %bx
41+
# INTEL: movrs bx, word ptr [2*rbp - 32]
42+
0x66,0x0f,0x38,0x8b,0x1c,0x6d,0xe0,0xff,0xff,0xff
43+
44+
# ATT: movrsw 127(%rcx), %bx
45+
# INTEL: movrs bx, word ptr [rcx + 127]
46+
0x66,0x0f,0x38,0x8b,0x59,0x7f
47+
48+
# ATT: movrsw -128(%rdx), %bx
49+
# INTEL: movrs bx, word ptr [rdx - 128]
50+
0x66,0x0f,0x38,0x8b,0x5a,0x80
51+
52+
# ATT: movrsl 268435456(%rbp,%r14,8), %ebx
53+
# INTEL: movrs ebx, dword ptr [rbp + 8*r14 + 268435456]
54+
0x42,0x0f,0x38,0x8b,0x9c,0xf5,0x00,0x00,0x00,0x10
55+
56+
# ATT: movrsl 291(%r8,%rax,4), %ebx
57+
# INTEL: movrs ebx, dword ptr [r8 + 4*rax + 291]
58+
0x41,0x0f,0x38,0x8b,0x9c,0x80,0x23,0x01,0x00,0x00
59+
60+
# ATT: movrsl (%rip), %ebx
61+
# INTEL: movrs ebx, dword ptr [rip]
62+
0x0f,0x38,0x8b,0x1d,0x00,0x00,0x00,0x00
63+
64+
# ATT: movrsl -32(,%rbp,2), %ebx
65+
# INTEL: movrs ebx, dword ptr [2*rbp - 32]
66+
0x0f,0x38,0x8b,0x1c,0x6d,0xe0,0xff,0xff,0xff
67+
68+
# ATT: movrsl 127(%rcx), %ebx
69+
# INTEL: movrs ebx, dword ptr [rcx + 127]
70+
0x0f,0x38,0x8b,0x59,0x7f
71+
72+
# ATT: movrsl -128(%rdx), %ebx
73+
# INTEL: movrs ebx, dword ptr [rdx - 128]
74+
0x0f,0x38,0x8b,0x5a,0x80
75+
76+
# ATT: movrsq 268435456(%rbp,%r14,8), %rbx
77+
# INTEL: movrs rbx, qword ptr [rbp + 8*r14 + 268435456]
78+
0x4a,0x0f,0x38,0x8b,0x9c,0xf5,0x00,0x00,0x00,0x10
79+
80+
# ATT: movrsq 291(%r8,%rax,4), %rbx
81+
# INTEL: movrs rbx, qword ptr [r8 + 4*rax + 291]
82+
0x49,0x0f,0x38,0x8b,0x9c,0x80,0x23,0x01,0x00,0x00
83+
84+
# ATT: movrsq (%rip), %rbx
85+
# INTEL: movrs rbx, qword ptr [rip]
86+
0x48,0x0f,0x38,0x8b,0x1d,0x00,0x00,0x00,0x00
87+
88+
# ATT: movrsq -32(,%rbp,2), %rbx
89+
# INTEL: movrs rbx, qword ptr [2*rbp - 32]
90+
0x48,0x0f,0x38,0x8b,0x1c,0x6d,0xe0,0xff,0xff,0xff
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# ATT: movrsq 127(%rcx), %rbx
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# INTEL: movrs rbx, qword ptr [rcx + 127]
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0x48,0x0f,0x38,0x8b,0x59,0x7f
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# ATT: movrsq -128(%rdx), %rbx
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# INTEL: movrs rbx, qword ptr [rdx - 128]
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0x48,0x0f,0x38,0x8b,0x5a,0x80

‎llvm/test/MC/Disassembler/X86/prefetchrst2-32.txt

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# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
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# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
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# ATT: prefetchrst2 268435456(%esp,%esi,8)
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# INTEL: prefetchrst2 byte ptr [esp + 8*esi + 268435456]
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0x0f,0x18,0xa4,0xf4,0x00,0x00,0x00,0x10
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# ATT: prefetchrst2 291(%edi,%eax,4)
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# INTEL: prefetchrst2 byte ptr [edi + 4*eax + 291]
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0x0f,0x18,0xa4,0x87,0x23,0x01,0x00,0x00
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# ATT: prefetchrst2 (%eax)
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# INTEL: prefetchrst2 byte ptr [eax]
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0x0f,0x18,0x20
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# ATT: prefetchrst2 -32(,%ebp,2)
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# INTEL: prefetchrst2 byte ptr [2*ebp - 32]
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0x0f,0x18,0x24,0x6d,0xe0,0xff,0xff,0xff
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# ATT: prefetchrst2 127(%ecx)
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# INTEL: prefetchrst2 byte ptr [ecx + 127]
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0x0f,0x18,0x61,0x7f
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# ATT: prefetchrst2 -128(%edx)
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# INTEL: prefetchrst2 byte ptr [edx - 128]
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0x0f,0x18,0x62,0x80

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