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[MIPS] Sign-extend subwords when expanding atomic max/min
In order for the following `SLT` instruction to work properly, we need to sign-extend appropriate subwords. In addition, subwords must remain in the same position from before sign-extension. Resolves #61881. Also, downstream bugs rust-lang/rust#100650 and rust-lang/rust#123772 are fixed.
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2 files changed

+109
-47
lines changed

2 files changed

+109
-47
lines changed

‎llvm/lib/Target/Mips/MipsExpandPseudo.cpp

+32-21
Original file line numberDiff line numberDiff line change
@@ -475,34 +475,45 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
475475

476476
// For little endian we need to clear uninterested bits.
477477
if (STI->isLittle()) {
478+
// If signed, we need to sign-extend.
478479
if (!IsUnsigned) {
479-
BuildMI(loopMBB, DL, TII->get(Mips::SRAV), OldVal)
480-
.addReg(OldVal)
481-
.addReg(ShiftAmnt);
482-
BuildMI(loopMBB, DL, TII->get(Mips::SRAV), Incr)
483-
.addReg(Incr)
484-
.addReg(ShiftAmnt);
485480
if (STI->hasMips32r2()) {
481+
BuildMI(loopMBB, DL, TII->get(Mips::SRAV), OldVal)
482+
.addReg(OldVal)
483+
.addReg(ShiftAmnt);
484+
BuildMI(loopMBB, DL, TII->get(Mips::SRAV), Incr)
485+
.addReg(Incr)
486+
.addReg(ShiftAmnt);
486487
BuildMI(loopMBB, DL, TII->get(SEOp), OldVal).addReg(OldVal);
487488
BuildMI(loopMBB, DL, TII->get(SEOp), Incr).addReg(Incr);
489+
BuildMI(loopMBB, DL, TII->get(Mips::SLLV), OldVal)
490+
.addReg(OldVal)
491+
.addReg(ShiftAmnt);
492+
BuildMI(loopMBB, DL, TII->get(Mips::SLLV), Incr)
493+
.addReg(Incr)
494+
.addReg(ShiftAmnt);
488495
} else {
489-
const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24;
490-
BuildMI(loopMBB, DL, TII->get(Mips::SLL), OldVal)
491-
.addReg(OldVal, RegState::Kill)
492-
.addImm(ShiftImm);
493-
BuildMI(loopMBB, DL, TII->get(Mips::SRA), OldVal)
494-
.addReg(OldVal, RegState::Kill)
495-
.addImm(ShiftImm);
496-
BuildMI(loopMBB, DL, TII->get(Mips::SLL), Incr)
497-
.addReg(Incr, RegState::Kill)
498-
.addImm(ShiftImm);
499-
BuildMI(loopMBB, DL, TII->get(Mips::SRA), Incr)
500-
.addReg(Incr, RegState::Kill)
501-
.addImm(ShiftImm);
496+
BuildMI(loopMBB, DL, TII->get(Mips::AND), OldVal)
497+
.addReg(OldVal)
498+
.addReg(Mask);
499+
BuildMI(loopMBB, DL, TII->get(Mips::AND), Incr)
500+
.addReg(Incr)
501+
.addReg(Mask);
502+
BuildMI(loopMBB, DL, TII->get(Mips::CLZ), Scratch4).addReg(Mask);
503+
BuildMI(loopMBB, DL, TII->get(Mips::SLLV), OldVal)
504+
.addReg(OldVal)
505+
.addReg(Scratch4);
506+
BuildMI(loopMBB, DL, TII->get(Mips::SRAV), OldVal)
507+
.addReg(OldVal)
508+
.addReg(Scratch4);
509+
BuildMI(loopMBB, DL, TII->get(Mips::SLLV), Incr)
510+
.addReg(Incr)
511+
.addReg(Scratch4);
512+
BuildMI(loopMBB, DL, TII->get(Mips::SRAV), Incr)
513+
.addReg(Incr)
514+
.addReg(Scratch4);
502515
}
503516
} else {
504-
// and OldVal, OldVal, Mask
505-
// and Incr, Incr, Mask
506517
BuildMI(loopMBB, DL, TII->get(Mips::AND), OldVal)
507518
.addReg(OldVal)
508519
.addReg(Mask);

‎llvm/test/CodeGen/Mips/atomic-min-max.ll

+77-26
Original file line numberDiff line numberDiff line change
@@ -1067,12 +1067,13 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) {
10671067
; MIPS32-NEXT: $BB4_1: # %entry
10681068
; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1
10691069
; MIPS32-NEXT: ll $2, 0($6)
1070-
; MIPS32-NEXT: srav $2, $2, $10
1071-
; MIPS32-NEXT: srav $7, $7, $10
1072-
; MIPS32-NEXT: sll $2, $2, 16
1073-
; MIPS32-NEXT: sra $2, $2, 16
1074-
; MIPS32-NEXT: sll $7, $7, 16
1075-
; MIPS32-NEXT: sra $7, $7, 16
1070+
; MIPS32-NEXT: and $2, $2, $8
1071+
; MIPS32-NEXT: and $7, $7, $8
1072+
; MIPS32-NEXT: clz $5, $8
1073+
; MIPS32-NEXT: sllv $2, $2, $5
1074+
; MIPS32-NEXT: srav $2, $2, $5
1075+
; MIPS32-NEXT: sllv $7, $7, $5
1076+
; MIPS32-NEXT: srav $7, $7, $5
10761077
; MIPS32-NEXT: slt $5, $2, $7
10771078
; MIPS32-NEXT: move $3, $2
10781079
; MIPS32-NEXT: movn $3, $7, $5
@@ -1095,7 +1096,6 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) {
10951096
; MIPS32-NEXT: addiu $sp, $sp, 8
10961097
; MIPS32-NEXT: jr $ra
10971098
; MIPS32-NEXT: nop
1098-
10991099
;
11001100
; MIPSEL-LABEL: test_max_16:
11011101
; MIPSEL: # %bb.0: # %entry
@@ -1118,6 +1118,8 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) {
11181118
; MIPSEL-NEXT: srav $7, $7, $10
11191119
; MIPSEL-NEXT: seh $2, $2
11201120
; MIPSEL-NEXT: seh $7, $7
1121+
; MIPSEL-NEXT: sllv $2, $2, $10
1122+
; MIPSEL-NEXT: sllv $7, $7, $10
11211123
; MIPSEL-NEXT: slt $5, $2, $7
11221124
; MIPSEL-NEXT: move $3, $2
11231125
; MIPSEL-NEXT: movn $3, $7, $5
@@ -1161,6 +1163,8 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) {
11611163
; MIPSELR6-NEXT: srav $7, $7, $10
11621164
; MIPSELR6-NEXT: seh $2, $2
11631165
; MIPSELR6-NEXT: seh $7, $7
1166+
; MIPSELR6-NEXT: sllv $2, $2, $10
1167+
; MIPSELR6-NEXT: sllv $7, $7, $10
11641168
; MIPSELR6-NEXT: slt $5, $2, $7
11651169
; MIPSELR6-NEXT: seleqz $3, $2, $5
11661170
; MIPSELR6-NEXT: selnez $5, $7, $5
@@ -1203,6 +1207,8 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) {
12031207
; MMEL-NEXT: srav $7, $7, $10
12041208
; MMEL-NEXT: seh $2, $2
12051209
; MMEL-NEXT: seh $7, $7
1210+
; MMEL-NEXT: sllv $2, $2, $10
1211+
; MMEL-NEXT: sllv $7, $7, $10
12061212
; MMEL-NEXT: slt $5, $2, $7
12071213
; MMEL-NEXT: or $3, $2, $zero
12081214
; MMEL-NEXT: movn $3, $7, $5
@@ -1244,6 +1250,8 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) {
12441250
; MMELR6-NEXT: srav $7, $7, $10
12451251
; MMELR6-NEXT: seh $2, $2
12461252
; MMELR6-NEXT: seh $7, $7
1253+
; MMELR6-NEXT: sllv $2, $2, $10
1254+
; MMELR6-NEXT: sllv $7, $7, $10
12471255
; MMELR6-NEXT: slt $5, $2, $7
12481256
; MMELR6-NEXT: seleqz $3, $2, $5
12491257
; MMELR6-NEXT: selnez $5, $7, $5
@@ -1365,6 +1373,8 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) {
13651373
; MIPS64EL-NEXT: srav $7, $7, $10
13661374
; MIPS64EL-NEXT: seh $2, $2
13671375
; MIPS64EL-NEXT: seh $7, $7
1376+
; MIPS64EL-NEXT: sllv $2, $2, $10
1377+
; MIPS64EL-NEXT: sllv $7, $7, $10
13681378
; MIPS64EL-NEXT: slt $5, $2, $7
13691379
; MIPS64EL-NEXT: move $3, $2
13701380
; MIPS64EL-NEXT: movn $3, $7, $5
@@ -1408,6 +1418,8 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) {
14081418
; MIPS64ELR6-NEXT: srav $7, $7, $10
14091419
; MIPS64ELR6-NEXT: seh $2, $2
14101420
; MIPS64ELR6-NEXT: seh $7, $7
1421+
; MIPS64ELR6-NEXT: sllv $2, $2, $10
1422+
; MIPS64ELR6-NEXT: sllv $7, $7, $10
14111423
; MIPS64ELR6-NEXT: slt $5, $2, $7
14121424
; MIPS64ELR6-NEXT: seleqz $3, $2, $5
14131425
; MIPS64ELR6-NEXT: selnez $5, $7, $5
@@ -1428,6 +1440,7 @@ define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) {
14281440
; MIPS64ELR6-NEXT: sync
14291441
; MIPS64ELR6-NEXT: daddiu $sp, $sp, 16
14301442
; MIPS64ELR6-NEXT: jrc $ra
1443+
14311444
entry:
14321445
%0 = atomicrmw max ptr %ptr, i16 %val seq_cst
14331446
ret i16 %0
@@ -1607,12 +1620,13 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) {
16071620
; MIPS32-NEXT: $BB5_1: # %entry
16081621
; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1
16091622
; MIPS32-NEXT: ll $2, 0($6)
1610-
; MIPS32-NEXT: srav $2, $2, $10
1611-
; MIPS32-NEXT: srav $7, $7, $10
1612-
; MIPS32-NEXT: sll $2, $2, 16
1613-
; MIPS32-NEXT: sra $2, $2, 16
1614-
; MIPS32-NEXT: sll $7, $7, 16
1615-
; MIPS32-NEXT: sra $7, $7, 16
1623+
; MIPS32-NEXT: and $2, $2, $8
1624+
; MIPS32-NEXT: and $7, $7, $8
1625+
; MIPS32-NEXT: clz $5, $8
1626+
; MIPS32-NEXT: sllv $2, $2, $5
1627+
; MIPS32-NEXT: srav $2, $2, $5
1628+
; MIPS32-NEXT: sllv $7, $7, $5
1629+
; MIPS32-NEXT: srav $7, $7, $5
16161630
; MIPS32-NEXT: slt $5, $2, $7
16171631
; MIPS32-NEXT: move $3, $2
16181632
; MIPS32-NEXT: movz $3, $7, $5
@@ -1657,6 +1671,8 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) {
16571671
; MIPSEL-NEXT: srav $7, $7, $10
16581672
; MIPSEL-NEXT: seh $2, $2
16591673
; MIPSEL-NEXT: seh $7, $7
1674+
; MIPSEL-NEXT: sllv $2, $2, $10
1675+
; MIPSEL-NEXT: sllv $7, $7, $10
16601676
; MIPSEL-NEXT: slt $5, $2, $7
16611677
; MIPSEL-NEXT: move $3, $2
16621678
; MIPSEL-NEXT: movz $3, $7, $5
@@ -1700,6 +1716,8 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) {
17001716
; MIPSELR6-NEXT: srav $7, $7, $10
17011717
; MIPSELR6-NEXT: seh $2, $2
17021718
; MIPSELR6-NEXT: seh $7, $7
1719+
; MIPSELR6-NEXT: sllv $2, $2, $10
1720+
; MIPSELR6-NEXT: sllv $7, $7, $10
17031721
; MIPSELR6-NEXT: slt $5, $2, $7
17041722
; MIPSELR6-NEXT: selnez $3, $2, $5
17051723
; MIPSELR6-NEXT: seleqz $5, $7, $5
@@ -1742,6 +1760,8 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) {
17421760
; MMEL-NEXT: srav $7, $7, $10
17431761
; MMEL-NEXT: seh $2, $2
17441762
; MMEL-NEXT: seh $7, $7
1763+
; MMEL-NEXT: sllv $2, $2, $10
1764+
; MMEL-NEXT: sllv $7, $7, $10
17451765
; MMEL-NEXT: slt $5, $2, $7
17461766
; MMEL-NEXT: or $3, $2, $zero
17471767
; MMEL-NEXT: movz $3, $7, $5
@@ -1783,6 +1803,8 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) {
17831803
; MMELR6-NEXT: srav $7, $7, $10
17841804
; MMELR6-NEXT: seh $2, $2
17851805
; MMELR6-NEXT: seh $7, $7
1806+
; MMELR6-NEXT: sllv $2, $2, $10
1807+
; MMELR6-NEXT: sllv $7, $7, $10
17861808
; MMELR6-NEXT: slt $5, $2, $7
17871809
; MMELR6-NEXT: selnez $3, $2, $5
17881810
; MMELR6-NEXT: seleqz $5, $7, $5
@@ -1904,6 +1926,8 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) {
19041926
; MIPS64EL-NEXT: srav $7, $7, $10
19051927
; MIPS64EL-NEXT: seh $2, $2
19061928
; MIPS64EL-NEXT: seh $7, $7
1929+
; MIPS64EL-NEXT: sllv $2, $2, $10
1930+
; MIPS64EL-NEXT: sllv $7, $7, $10
19071931
; MIPS64EL-NEXT: slt $5, $2, $7
19081932
; MIPS64EL-NEXT: move $3, $2
19091933
; MIPS64EL-NEXT: movz $3, $7, $5
@@ -1947,6 +1971,8 @@ define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) {
19471971
; MIPS64ELR6-NEXT: srav $7, $7, $10
19481972
; MIPS64ELR6-NEXT: seh $2, $2
19491973
; MIPS64ELR6-NEXT: seh $7, $7
1974+
; MIPS64ELR6-NEXT: sllv $2, $2, $10
1975+
; MIPS64ELR6-NEXT: sllv $7, $7, $10
19501976
; MIPS64ELR6-NEXT: slt $5, $2, $7
19511977
; MIPS64ELR6-NEXT: selnez $3, $2, $5
19521978
; MIPS64ELR6-NEXT: seleqz $5, $7, $5
@@ -2694,7 +2720,6 @@ define i16 @test_umin_16(ptr nocapture %ptr, i16 signext %val) {
26942720
; MIPS32-NEXT: jr $ra
26952721
; MIPS32-NEXT: nop
26962722
;
2697-
;
26982723
; MIPSEL-LABEL: test_umin_16:
26992724
; MIPSEL: # %bb.0: # %entry
27002725
; MIPSEL-NEXT: addiu $sp, $sp, -8
@@ -3194,12 +3219,13 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) {
31943219
; MIPS32-NEXT: $BB8_1: # %entry
31953220
; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1
31963221
; MIPS32-NEXT: ll $2, 0($6)
3197-
; MIPS32-NEXT: srav $2, $2, $10
3198-
; MIPS32-NEXT: srav $7, $7, $10
3199-
; MIPS32-NEXT: sll $2, $2, 24
3200-
; MIPS32-NEXT: sra $2, $2, 24
3201-
; MIPS32-NEXT: sll $7, $7, 24
3202-
; MIPS32-NEXT: sra $7, $7, 24
3222+
; MIPS32-NEXT: and $2, $2, $8
3223+
; MIPS32-NEXT: and $7, $7, $8
3224+
; MIPS32-NEXT: clz $5, $8
3225+
; MIPS32-NEXT: sllv $2, $2, $5
3226+
; MIPS32-NEXT: srav $2, $2, $5
3227+
; MIPS32-NEXT: sllv $7, $7, $5
3228+
; MIPS32-NEXT: srav $7, $7, $5
32033229
; MIPS32-NEXT: slt $5, $2, $7
32043230
; MIPS32-NEXT: move $3, $2
32053231
; MIPS32-NEXT: movn $3, $7, $5
@@ -3244,6 +3270,8 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) {
32443270
; MIPSEL-NEXT: srav $7, $7, $10
32453271
; MIPSEL-NEXT: seb $2, $2
32463272
; MIPSEL-NEXT: seb $7, $7
3273+
; MIPSEL-NEXT: sllv $2, $2, $10
3274+
; MIPSEL-NEXT: sllv $7, $7, $10
32473275
; MIPSEL-NEXT: slt $5, $2, $7
32483276
; MIPSEL-NEXT: move $3, $2
32493277
; MIPSEL-NEXT: movn $3, $7, $5
@@ -3287,6 +3315,8 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) {
32873315
; MIPSELR6-NEXT: srav $7, $7, $10
32883316
; MIPSELR6-NEXT: seb $2, $2
32893317
; MIPSELR6-NEXT: seb $7, $7
3318+
; MIPSELR6-NEXT: sllv $2, $2, $10
3319+
; MIPSELR6-NEXT: sllv $7, $7, $10
32903320
; MIPSELR6-NEXT: slt $5, $2, $7
32913321
; MIPSELR6-NEXT: seleqz $3, $2, $5
32923322
; MIPSELR6-NEXT: selnez $5, $7, $5
@@ -3329,6 +3359,8 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) {
33293359
; MMEL-NEXT: srav $7, $7, $10
33303360
; MMEL-NEXT: seb $2, $2
33313361
; MMEL-NEXT: seb $7, $7
3362+
; MMEL-NEXT: sllv $2, $2, $10
3363+
; MMEL-NEXT: sllv $7, $7, $10
33323364
; MMEL-NEXT: slt $5, $2, $7
33333365
; MMEL-NEXT: or $3, $2, $zero
33343366
; MMEL-NEXT: movn $3, $7, $5
@@ -3370,6 +3402,8 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) {
33703402
; MMELR6-NEXT: srav $7, $7, $10
33713403
; MMELR6-NEXT: seb $2, $2
33723404
; MMELR6-NEXT: seb $7, $7
3405+
; MMELR6-NEXT: sllv $2, $2, $10
3406+
; MMELR6-NEXT: sllv $7, $7, $10
33733407
; MMELR6-NEXT: slt $5, $2, $7
33743408
; MMELR6-NEXT: seleqz $3, $2, $5
33753409
; MMELR6-NEXT: selnez $5, $7, $5
@@ -3491,6 +3525,8 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) {
34913525
; MIPS64EL-NEXT: srav $7, $7, $10
34923526
; MIPS64EL-NEXT: seb $2, $2
34933527
; MIPS64EL-NEXT: seb $7, $7
3528+
; MIPS64EL-NEXT: sllv $2, $2, $10
3529+
; MIPS64EL-NEXT: sllv $7, $7, $10
34943530
; MIPS64EL-NEXT: slt $5, $2, $7
34953531
; MIPS64EL-NEXT: move $3, $2
34963532
; MIPS64EL-NEXT: movn $3, $7, $5
@@ -3534,6 +3570,8 @@ define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) {
35343570
; MIPS64ELR6-NEXT: srav $7, $7, $10
35353571
; MIPS64ELR6-NEXT: seb $2, $2
35363572
; MIPS64ELR6-NEXT: seb $7, $7
3573+
; MIPS64ELR6-NEXT: sllv $2, $2, $10
3574+
; MIPS64ELR6-NEXT: sllv $7, $7, $10
35373575
; MIPS64ELR6-NEXT: slt $5, $2, $7
35383576
; MIPS64ELR6-NEXT: seleqz $3, $2, $5
35393577
; MIPS64ELR6-NEXT: selnez $5, $7, $5
@@ -3733,12 +3771,13 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) {
37333771
; MIPS32-NEXT: $BB9_1: # %entry
37343772
; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1
37353773
; MIPS32-NEXT: ll $2, 0($6)
3736-
; MIPS32-NEXT: srav $2, $2, $10
3737-
; MIPS32-NEXT: srav $7, $7, $10
3738-
; MIPS32-NEXT: sll $2, $2, 24
3739-
; MIPS32-NEXT: sra $2, $2, 24
3740-
; MIPS32-NEXT: sll $7, $7, 24
3741-
; MIPS32-NEXT: sra $7, $7, 24
3774+
; MIPS32-NEXT: and $2, $2, $8
3775+
; MIPS32-NEXT: and $7, $7, $8
3776+
; MIPS32-NEXT: clz $5, $8
3777+
; MIPS32-NEXT: sllv $2, $2, $5
3778+
; MIPS32-NEXT: srav $2, $2, $5
3779+
; MIPS32-NEXT: sllv $7, $7, $5
3780+
; MIPS32-NEXT: srav $7, $7, $5
37423781
; MIPS32-NEXT: slt $5, $2, $7
37433782
; MIPS32-NEXT: move $3, $2
37443783
; MIPS32-NEXT: movz $3, $7, $5
@@ -3783,6 +3822,8 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) {
37833822
; MIPSEL-NEXT: srav $7, $7, $10
37843823
; MIPSEL-NEXT: seb $2, $2
37853824
; MIPSEL-NEXT: seb $7, $7
3825+
; MIPSEL-NEXT: sllv $2, $2, $10
3826+
; MIPSEL-NEXT: sllv $7, $7, $10
37863827
; MIPSEL-NEXT: slt $5, $2, $7
37873828
; MIPSEL-NEXT: move $3, $2
37883829
; MIPSEL-NEXT: movz $3, $7, $5
@@ -3826,6 +3867,8 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) {
38263867
; MIPSELR6-NEXT: srav $7, $7, $10
38273868
; MIPSELR6-NEXT: seb $2, $2
38283869
; MIPSELR6-NEXT: seb $7, $7
3870+
; MIPSELR6-NEXT: sllv $2, $2, $10
3871+
; MIPSELR6-NEXT: sllv $7, $7, $10
38293872
; MIPSELR6-NEXT: slt $5, $2, $7
38303873
; MIPSELR6-NEXT: selnez $3, $2, $5
38313874
; MIPSELR6-NEXT: seleqz $5, $7, $5
@@ -3868,6 +3911,8 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) {
38683911
; MMEL-NEXT: srav $7, $7, $10
38693912
; MMEL-NEXT: seb $2, $2
38703913
; MMEL-NEXT: seb $7, $7
3914+
; MMEL-NEXT: sllv $2, $2, $10
3915+
; MMEL-NEXT: sllv $7, $7, $10
38713916
; MMEL-NEXT: slt $5, $2, $7
38723917
; MMEL-NEXT: or $3, $2, $zero
38733918
; MMEL-NEXT: movz $3, $7, $5
@@ -3909,6 +3954,8 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) {
39093954
; MMELR6-NEXT: srav $7, $7, $10
39103955
; MMELR6-NEXT: seb $2, $2
39113956
; MMELR6-NEXT: seb $7, $7
3957+
; MMELR6-NEXT: sllv $2, $2, $10
3958+
; MMELR6-NEXT: sllv $7, $7, $10
39123959
; MMELR6-NEXT: slt $5, $2, $7
39133960
; MMELR6-NEXT: selnez $3, $2, $5
39143961
; MMELR6-NEXT: seleqz $5, $7, $5
@@ -4030,6 +4077,8 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) {
40304077
; MIPS64EL-NEXT: srav $7, $7, $10
40314078
; MIPS64EL-NEXT: seb $2, $2
40324079
; MIPS64EL-NEXT: seb $7, $7
4080+
; MIPS64EL-NEXT: sllv $2, $2, $10
4081+
; MIPS64EL-NEXT: sllv $7, $7, $10
40334082
; MIPS64EL-NEXT: slt $5, $2, $7
40344083
; MIPS64EL-NEXT: move $3, $2
40354084
; MIPS64EL-NEXT: movz $3, $7, $5
@@ -4073,6 +4122,8 @@ define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) {
40734122
; MIPS64ELR6-NEXT: srav $7, $7, $10
40744123
; MIPS64ELR6-NEXT: seb $2, $2
40754124
; MIPS64ELR6-NEXT: seb $7, $7
4125+
; MIPS64ELR6-NEXT: sllv $2, $2, $10
4126+
; MIPS64ELR6-NEXT: sllv $7, $7, $10
40764127
; MIPS64ELR6-NEXT: slt $5, $2, $7
40774128
; MIPS64ELR6-NEXT: selnez $3, $2, $5
40784129
; MIPS64ELR6-NEXT: seleqz $5, $7, $5

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