Skip to content

Commit 9af1f8f

Browse files
jacquesguanjacquesguan
authored
[RISCV] Match vector fp-int convert intrinsics with specific RTZ rounding mode to the rtz variants (#98120)
1 parent 6647011 commit 9af1f8f

File tree

7 files changed

+219
-0
lines changed

7 files changed

+219
-0
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3957,6 +3957,28 @@ class VPatUnaryNoMaskRoundingMode<string intrinsic_name,
39573957
(XLenVT timm:$round),
39583958
GPR:$vl, log2sew, TU_MU)>;
39593959

3960+
class VPatUnaryNoMaskRTZ<string intrinsic_name,
3961+
string inst,
3962+
string kind,
3963+
ValueType result_type,
3964+
ValueType op2_type,
3965+
int log2sew,
3966+
LMULInfo vlmul,
3967+
VReg result_reg_class,
3968+
VReg op2_reg_class,
3969+
bit isSEWAware = 0> :
3970+
Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
3971+
(result_type result_reg_class:$merge),
3972+
(op2_type op2_reg_class:$rs2),
3973+
(XLenVT 0b001),
3974+
VLOpFrag)),
3975+
(!cast<Instruction>(
3976+
!if(isSEWAware,
3977+
inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew),
3978+
inst#"_"#kind#"_"#vlmul.MX))
3979+
(result_type result_reg_class:$merge),
3980+
(op2_type op2_reg_class:$rs2),
3981+
GPR:$vl, log2sew, TU_MU)>;
39603982

39613983
class VPatUnaryMask<string intrinsic_name,
39623984
string inst,
@@ -4009,6 +4031,31 @@ class VPatUnaryMaskRoundingMode<string intrinsic_name,
40094031
(XLenVT timm:$round),
40104032
GPR:$vl, log2sew, (XLenVT timm:$policy))>;
40114033

4034+
class VPatUnaryMaskRTZ<string intrinsic_name,
4035+
string inst,
4036+
string kind,
4037+
ValueType result_type,
4038+
ValueType op2_type,
4039+
ValueType mask_type,
4040+
int log2sew,
4041+
LMULInfo vlmul,
4042+
VReg result_reg_class,
4043+
VReg op2_reg_class,
4044+
bit isSEWAware = 0> :
4045+
Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
4046+
(result_type result_reg_class:$merge),
4047+
(op2_type op2_reg_class:$rs2),
4048+
(mask_type V0),
4049+
(XLenVT 0b001),
4050+
VLOpFrag, (XLenVT timm:$policy))),
4051+
(!cast<Instruction>(
4052+
!if(isSEWAware,
4053+
inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",
4054+
inst#"_"#kind#"_"#vlmul.MX#"_MASK"))
4055+
(result_type result_reg_class:$merge),
4056+
(op2_type op2_reg_class:$rs2),
4057+
(mask_type V0),
4058+
GPR:$vl, log2sew, (XLenVT timm:$policy))>;
40124059

40134060
class VPatMaskUnaryNoMask<string intrinsic_name,
40144061
string inst,
@@ -4826,6 +4873,25 @@ multiclass VPatConversionRoundingMode<string intrinsic,
48264873
op1_reg_class, isSEWAware>;
48274874
}
48284875

4876+
multiclass VPatConversionRTZ<string intrinsic,
4877+
string inst,
4878+
string kind,
4879+
ValueType result_type,
4880+
ValueType op1_type,
4881+
ValueType mask_type,
4882+
int log2sew,
4883+
LMULInfo vlmul,
4884+
VReg result_reg_class,
4885+
VReg op1_reg_class,
4886+
bit isSEWAware = 0> {
4887+
def : VPatUnaryNoMaskRTZ<intrinsic, inst, kind, result_type, op1_type,
4888+
log2sew, vlmul, result_reg_class,
4889+
op1_reg_class, isSEWAware>;
4890+
def : VPatUnaryMaskRTZ<intrinsic, inst, kind, result_type, op1_type,
4891+
mask_type, log2sew, vlmul, result_reg_class,
4892+
op1_reg_class, isSEWAware>;
4893+
}
4894+
48294895
multiclass VPatBinaryV_VV<string intrinsic, string instruction,
48304896
list<VTypeInfo> vtilist, bit isSEWAware = 0> {
48314897
foreach vti = vtilist in
@@ -5776,6 +5842,18 @@ multiclass VPatConversionVI_VF_RM<string intrinsic,
57765842
}
57775843
}
57785844

5845+
multiclass VPatConversionVI_VF_RTZ<string intrinsic,
5846+
string instruction> {
5847+
foreach fvti = AllFloatVectors in {
5848+
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
5849+
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
5850+
GetVTypePredicates<ivti>.Predicates) in
5851+
defm : VPatConversionRTZ<intrinsic, instruction, "V",
5852+
ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
5853+
fvti.LMul, ivti.RegClass, fvti.RegClass>;
5854+
}
5855+
}
5856+
57795857
multiclass VPatConversionVF_VI_RM<string intrinsic, string instruction,
57805858
bit isSEWAware = 0> {
57815859
foreach fvti = AllFloatVectors in {
@@ -5813,6 +5891,18 @@ multiclass VPatConversionWI_VF_RM<string intrinsic, string instruction> {
58135891
}
58145892
}
58155893

5894+
multiclass VPatConversionWI_VF_RTZ<string intrinsic, string instruction> {
5895+
foreach fvtiToFWti = AllWidenableFloatVectors in {
5896+
defvar fvti = fvtiToFWti.Vti;
5897+
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
5898+
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
5899+
GetVTypePredicates<iwti>.Predicates) in
5900+
defm : VPatConversionRTZ<intrinsic, instruction, "V",
5901+
iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,
5902+
fvti.LMul, iwti.RegClass, fvti.RegClass>;
5903+
}
5904+
}
5905+
58165906
multiclass VPatConversionWF_VI<string intrinsic, string instruction,
58175907
bit isSEWAware = 0> {
58185908
foreach vtiToWti = AllWidenableIntToFloatVectors in {
@@ -5879,6 +5969,18 @@ multiclass VPatConversionVI_WF_RM <string intrinsic, string instruction> {
58795969
}
58805970
}
58815971

5972+
multiclass VPatConversionVI_WF_RTZ <string intrinsic, string instruction> {
5973+
foreach vtiToWti = AllWidenableIntToFloatVectors in {
5974+
defvar vti = vtiToWti.Vti;
5975+
defvar fwti = vtiToWti.Wti;
5976+
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
5977+
GetVTypePredicates<fwti>.Predicates) in
5978+
defm : VPatConversionRTZ<intrinsic, instruction, "W",
5979+
vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,
5980+
vti.LMul, vti.RegClass, fwti.RegClass>;
5981+
}
5982+
}
5983+
58825984
multiclass VPatConversionVF_WI_RM <string intrinsic, string instruction,
58835985
bit isSEWAware = 0> {
58845986
foreach fvtiToFWti = AllWidenableFloatVectors in {
@@ -5921,6 +6023,20 @@ multiclass VPatConversionVF_WF_RM<string intrinsic, string instruction,
59216023
}
59226024
}
59236025

6026+
multiclass VPatConversionVF_WF_RTZ<string intrinsic, string instruction,
6027+
list<VTypeInfoToWide> wlist = AllWidenableFloatVectors,
6028+
bit isSEWAware = 0> {
6029+
foreach fvtiToFWti = wlist in {
6030+
defvar fvti = fvtiToFWti.Vti;
6031+
defvar fwti = fvtiToFWti.Wti;
6032+
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
6033+
GetVTypePredicates<fwti>.Predicates) in
6034+
defm : VPatConversionRTZ<intrinsic, instruction, "W",
6035+
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
6036+
fvti.LMul, fvti.RegClass, fwti.RegClass, isSEWAware>;
6037+
}
6038+
}
6039+
59246040
multiclass VPatConversionVF_WF_BF_RM<string intrinsic, string instruction,
59256041
bit isSEWAware = 0> {
59266042
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
@@ -7153,6 +7269,8 @@ foreach fvti = AllFloatVectors in {
71537269
//===----------------------------------------------------------------------===//
71547270
// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
71557271
//===----------------------------------------------------------------------===//
7272+
defm : VPatConversionVI_VF_RTZ<"int_riscv_vfcvt_x_f_v", "PseudoVFCVT_RTZ_X_F">;
7273+
defm : VPatConversionVI_VF_RTZ<"int_riscv_vfcvt_xu_f_v", "PseudoVFCVT_RTZ_XU_F">;
71567274
defm : VPatConversionVI_VF_RM<"int_riscv_vfcvt_x_f_v", "PseudoVFCVT_X_F">;
71577275
defm : VPatConversionVI_VF_RM<"int_riscv_vfcvt_xu_f_v", "PseudoVFCVT_XU_F">;
71587276
defm : VPatConversionVI_VF<"int_riscv_vfcvt_rtz_xu_f_v", "PseudoVFCVT_RTZ_XU_F">;
@@ -7165,6 +7283,8 @@ defm : VPatConversionVF_VI_RM<"int_riscv_vfcvt_f_xu_v", "PseudoVFCVT_F_XU",
71657283
//===----------------------------------------------------------------------===//
71667284
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
71677285
//===----------------------------------------------------------------------===//
7286+
defm : VPatConversionWI_VF_RTZ<"int_riscv_vfwcvt_xu_f_v", "PseudoVFWCVT_RTZ_XU_F">;
7287+
defm : VPatConversionWI_VF_RTZ<"int_riscv_vfwcvt_x_f_v", "PseudoVFWCVT_RTZ_X_F">;
71687288
defm : VPatConversionWI_VF_RM<"int_riscv_vfwcvt_xu_f_v", "PseudoVFWCVT_XU_F">;
71697289
defm : VPatConversionWI_VF_RM<"int_riscv_vfwcvt_x_f_v", "PseudoVFWCVT_X_F">;
71707290
defm : VPatConversionWI_VF<"int_riscv_vfwcvt_rtz_xu_f_v", "PseudoVFWCVT_RTZ_XU_F">;
@@ -7181,6 +7301,8 @@ defm : VPatConversionWF_VF_BF<"int_riscv_vfwcvtbf16_f_f_v",
71817301
//===----------------------------------------------------------------------===//
71827302
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
71837303
//===----------------------------------------------------------------------===//
7304+
defm : VPatConversionVI_WF_RTZ<"int_riscv_vfncvt_xu_f_w", "PseudoVFNCVT_RTZ_XU_F">;
7305+
defm : VPatConversionVI_WF_RTZ<"int_riscv_vfncvt_x_f_w", "PseudoVFNCVT_RTZ_X_F">;
71847306
defm : VPatConversionVI_WF_RM<"int_riscv_vfncvt_xu_f_w", "PseudoVFNCVT_XU_F">;
71857307
defm : VPatConversionVI_WF_RM<"int_riscv_vfncvt_x_f_w", "PseudoVFNCVT_X_F">;
71867308
defm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_xu_f_w", "PseudoVFNCVT_RTZ_XU_F">;

‎llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -693,3 +693,19 @@ entry:
693693

694694
ret <vscale x 8 x i64> %a
695695
}
696+
697+
define <vscale x 8 x i64> @intrinsic_vfcvt_mask_x.f.v_rtz_nxv8i64_nxv8f64(<vscale x 8 x i64> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
698+
; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_rtz_nxv8i64_nxv8f64:
699+
; CHECK: # %bb.0: # %entry
700+
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
701+
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v16, v0.t
702+
; CHECK-NEXT: ret
703+
entry:
704+
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64(
705+
<vscale x 8 x i64> %0,
706+
<vscale x 8 x double> %1,
707+
<vscale x 8 x i1> %2,
708+
iXLen 1, iXLen %3, iXLen 1)
709+
710+
ret <vscale x 8 x i64> %a
711+
}

‎llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -693,3 +693,19 @@ entry:
693693

694694
ret <vscale x 8 x i64> %a
695695
}
696+
697+
define <vscale x 8 x i64> @intrinsic_vfcvt_mask_xu.f.v_rtz_nxv8i64_nxv8f64(<vscale x 8 x i64> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
698+
; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_rtz_nxv8i64_nxv8f64:
699+
; CHECK: # %bb.0: # %entry
700+
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
701+
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v16, v0.t
702+
; CHECK-NEXT: ret
703+
entry:
704+
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64(
705+
<vscale x 8 x i64> %0,
706+
<vscale x 8 x double> %1,
707+
<vscale x 8 x i1> %2,
708+
iXLen 1, iXLen %3, iXLen 1)
709+
710+
ret <vscale x 8 x i64> %a
711+
}

‎llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -708,3 +708,20 @@ entry:
708708

709709
ret <vscale x 8 x i32> %a
710710
}
711+
712+
define <vscale x 8 x i32> @intrinsic_vfncvt_mask_x.f.w_rtz_nxv8i32_nxv8f64(<vscale x 8 x i32> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
713+
; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_rtz_nxv8i32_nxv8f64:
714+
; CHECK: # %bb.0: # %entry
715+
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
716+
; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16, v0.t
717+
; CHECK-NEXT: ret
718+
entry:
719+
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64(
720+
<vscale x 8 x i32> %0,
721+
<vscale x 8 x double> %1,
722+
<vscale x 8 x i1> %2,
723+
iXLen 1, iXLen %3, iXLen 1)
724+
725+
ret <vscale x 8 x i32> %a
726+
}
727+

‎llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -708,3 +708,19 @@ entry:
708708

709709
ret <vscale x 8 x i32> %a
710710
}
711+
712+
define <vscale x 8 x i32> @intrinsic_vfncvt_mask_xu.f.w_rtz_nxv8i32_nxv8f64(<vscale x 8 x i32> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
713+
; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_rtz_nxv8i32_nxv8f64:
714+
; CHECK: # %bb.0: # %entry
715+
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
716+
; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16, v0.t
717+
; CHECK-NEXT: ret
718+
entry:
719+
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64(
720+
<vscale x 8 x i32> %0,
721+
<vscale x 8 x double> %1,
722+
<vscale x 8 x i1> %2,
723+
iXLen 1, iXLen %3, iXLen 1)
724+
725+
ret <vscale x 8 x i32> %a
726+
}

‎llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -426,3 +426,19 @@ entry:
426426

427427
ret <vscale x 8 x i64> %a
428428
}
429+
430+
define <vscale x 8 x i64> @intrinsic_vfwcvt_mask_x.f.v_rtz_nxv8i64_nxv8f32(<vscale x 8 x i64> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
431+
; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_rtz_nxv8i64_nxv8f32:
432+
; CHECK: # %bb.0: # %entry
433+
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
434+
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v16, v0.t
435+
; CHECK-NEXT: ret
436+
entry:
437+
%a = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32(
438+
<vscale x 8 x i64> %0,
439+
<vscale x 8 x float> %1,
440+
<vscale x 8 x i1> %2,
441+
iXLen 1, iXLen %3, iXLen 1)
442+
443+
ret <vscale x 8 x i64> %a
444+
}

‎llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -426,3 +426,19 @@ entry:
426426

427427
ret <vscale x 8 x i64> %a
428428
}
429+
430+
define <vscale x 8 x i64> @intrinsic_vfwcvt_mask_xu.f.v_rtz_nxv8i64_nxv8f32(<vscale x 8 x i64> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
431+
; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_rtz_nxv8i64_nxv8f32:
432+
; CHECK: # %bb.0: # %entry
433+
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
434+
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v16, v0.t
435+
; CHECK-NEXT: ret
436+
entry:
437+
%a = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32(
438+
<vscale x 8 x i64> %0,
439+
<vscale x 8 x float> %1,
440+
<vscale x 8 x i1> %2,
441+
iXLen 1, iXLen %3, iXLen 1)
442+
443+
ret <vscale x 8 x i64> %a
444+
}

0 commit comments

Comments
 (0)