[RISCV] Handle zvfhmin promotion to f32 in half arith costs

Arithmetic half ops on zvfhmin will be promoted and carried out in f32, so this updates getArithmeticInstrCost to check for this.

Author: lukel97

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

@@ -1816,6 +1816,13 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
     return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
                                          Args, CxtI);
 
+  // On zvfhmin, f16 vectors may be promoted to f32.
+  // FIXME: nxv32f16 will be custom lowered and split.
+  unsigned ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
+  if (TLI->getOperationAction(ISDOpcode, LT.second) ==
+      TargetLoweringBase::LegalizeAction::Promote)
+    LT.second = TLI->getTypeToPromoteTo(ISDOpcode, LT.second);
+
   auto getConstantMatCost =
     [&](unsigned Operand, TTI::OperandValueInfo OpInfo) -> InstructionCost {
     if (OpInfo.isUniform() && TLI->canSplatOperand(Opcode, Operand))
@@ -1837,7 +1844,7 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
     ConstantMatCost += getConstantMatCost(1, Op2Info);
 
   unsigned Op;
-  switch (TLI->InstructionOpcodeToISD(Opcode)) {
+  switch (ISDOpcode) {
   case ISD::ADD:
   case ISD::SUB:
     Op = RISCV::VADD_VV;
@@ -1867,11 +1874,9 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
     break;
   case ISD::FADD:
   case ISD::FSUB:
-    // TODO: Address FP16 with VFHMIN
     Op = RISCV::VFADD_VV;
     break;
   case ISD::FMUL:
-    // TODO: Address FP16 with VFHMIN
     Op = RISCV::VFMUL_VV;
     break;
   case ISD::FDIV: