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[RISCV] Adjust RV64I data layout by using n32:64 in layout string
Although i32 type is illegal in the backend, RV64I has pretty good support for i32 types by using W instructions. By adding n32 to the DataLayout string, middle end optimizations will consider i32 to be a native type. One known effect of this is enabling LoopStrengthReduce on loops with i32 induction variables. This can be beneficial because C/C++ code often has loops with i32 induction variables due to the use of `int` or `unsigned int`. If this patch exposes performance issues, those are better addressed by tuning LSR or other passes. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D116735
1 parent 4b0c285 commit 974e2e6

10 files changed

+69
-63
lines changed

‎clang/lib/Basic/Targets/RISCV.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -140,7 +140,7 @@ class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo {
140140
: RISCVTargetInfo(Triple, Opts) {
141141
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
142142
IntMaxType = Int64Type = SignedLong;
143-
resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n64-S128");
143+
resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128");
144144
}
145145

146146
bool setABI(const std::string &Name) override {

‎llvm/docs/ReleaseNotes.rst

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,9 @@ Changes to the RISC-V Backend
119119

120120
* Support for the unratified Zbe, Zbf, Zbm, Zbp, Zbr, and Zbt extensions have
121121
been removed.
122+
* i32 is now a native type in the datalayout string. This enables
123+
LoopStrengthReduce for loops with i32 induction variables, among other
124+
optimizations.
122125

123126
Changes to the WebAssembly Backend
124127
----------------------------------

‎llvm/lib/IR/AutoUpgrade.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4847,6 +4847,14 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) {
48474847
return DL.empty() ? std::string("G1") : (DL + "-G1").str();
48484848
}
48494849

4850+
if (T.isRISCV64()) {
4851+
// Make i32 a native type for 64-bit RISC-V.
4852+
auto I = DL.find("-n64-");
4853+
if (I != StringRef::npos)
4854+
return (DL.take_front(I) + "-n32:64-" + DL.drop_front(I + 5)).str();
4855+
return DL.str();
4856+
}
4857+
48504858
std::string Res = DL.str();
48514859
if (!T.isX86())
48524860
return Res;

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
6969

7070
static StringRef computeDataLayout(const Triple &TT) {
7171
if (TT.isArch64Bit())
72-
return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
72+
return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
7373
assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
7474
return "e-m:e-p:32:32-i64:64-n32-S128";
7575
}

‎llvm/test/CodeGen/RISCV/aext-to-sext.ll

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -11,24 +11,21 @@
1111
define void @quux(i32 signext %arg, i32 signext %arg1) nounwind {
1212
; RV64I-LABEL: quux:
1313
; RV64I: # %bb.0: # %bb
14-
; RV64I-NEXT: addi sp, sp, -32
15-
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
16-
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
17-
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
14+
; RV64I-NEXT: addi sp, sp, -16
15+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
16+
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
1817
; RV64I-NEXT: beq a0, a1, .LBB0_3
1918
; RV64I-NEXT: # %bb.1: # %bb2.preheader
20-
; RV64I-NEXT: mv s0, a1
21-
; RV64I-NEXT: mv s1, a0
19+
; RV64I-NEXT: subw s0, a1, a0
2220
; RV64I-NEXT: .LBB0_2: # %bb2
2321
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
2422
; RV64I-NEXT: call hoge@plt
25-
; RV64I-NEXT: addiw s1, s1, 1
26-
; RV64I-NEXT: bne s1, s0, .LBB0_2
23+
; RV64I-NEXT: addiw s0, s0, -1
24+
; RV64I-NEXT: bnez s0, .LBB0_2
2725
; RV64I-NEXT: .LBB0_3: # %bb6
28-
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
29-
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
30-
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
31-
; RV64I-NEXT: addi sp, sp, 32
26+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
27+
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
28+
; RV64I-NEXT: addi sp, sp, 16
3229
; RV64I-NEXT: ret
3330
bb:
3431
%tmp = icmp eq i32 %arg, %arg1

‎llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll

Lines changed: 11 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -52,24 +52,20 @@ define void @test(i32 signext %i) nounwind {
5252
; RV64-LABEL: test:
5353
; RV64: # %bb.0: # %entry
5454
; RV64-NEXT: slliw a1, a0, 1
55-
; RV64-NEXT: lui a4, 2
56-
; RV64-NEXT: blt a4, a1, .LBB0_3
55+
; RV64-NEXT: lui a3, 2
56+
; RV64-NEXT: blt a3, a1, .LBB0_3
5757
; RV64-NEXT: # %bb.1: # %bb.preheader
58-
; RV64-NEXT: li a2, 0
59-
; RV64-NEXT: lui a3, %hi(flags2)
60-
; RV64-NEXT: addi a3, a3, %lo(flags2)
61-
; RV64-NEXT: addiw a4, a4, 1
58+
; RV64-NEXT: lui a2, %hi(flags2)
59+
; RV64-NEXT: addi a2, a2, %lo(flags2)
60+
; RV64-NEXT: addiw a3, a3, 1
6261
; RV64-NEXT: .LBB0_2: # %bb
6362
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
64-
; RV64-NEXT: mulw a5, a2, a0
65-
; RV64-NEXT: addw a5, a5, a1
66-
; RV64-NEXT: slli a6, a5, 32
67-
; RV64-NEXT: srli a6, a6, 32
68-
; RV64-NEXT: add a6, a3, a6
69-
; RV64-NEXT: sb zero, 0(a6)
70-
; RV64-NEXT: addw a5, a5, a0
71-
; RV64-NEXT: addiw a2, a2, 1
72-
; RV64-NEXT: blt a5, a4, .LBB0_2
63+
; RV64-NEXT: slli a4, a1, 32
64+
; RV64-NEXT: srli a4, a4, 32
65+
; RV64-NEXT: add a4, a2, a4
66+
; RV64-NEXT: addw a1, a1, a0
67+
; RV64-NEXT: sb zero, 0(a4)
68+
; RV64-NEXT: blt a1, a3, .LBB0_2
7369
; RV64-NEXT: .LBB0_3: # %return
7470
; RV64-NEXT: ret
7571
entry:

‎llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll

Lines changed: 14 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -53,25 +53,24 @@ define void @test(i32 signext %row, i32 signext %N.in) nounwind {
5353
; RV64: # %bb.0: # %entry
5454
; RV64-NEXT: blez a1, .LBB0_3
5555
; RV64-NEXT: # %bb.1: # %cond_true.preheader
56-
; RV64-NEXT: li a4, 0
56+
; RV64-NEXT: li a2, 0
5757
; RV64-NEXT: slli a0, a0, 6
58-
; RV64-NEXT: lui a2, %hi(A)
59-
; RV64-NEXT: addi a2, a2, %lo(A)
60-
; RV64-NEXT: add a0, a2, a0
61-
; RV64-NEXT: li a2, 4
62-
; RV64-NEXT: li a3, 5
58+
; RV64-NEXT: lui a3, %hi(A)
59+
; RV64-NEXT: addi a3, a3, %lo(A)
60+
; RV64-NEXT: add a0, a3, a0
61+
; RV64-NEXT: addi a3, a0, 4
62+
; RV64-NEXT: li a4, 4
63+
; RV64-NEXT: li a5, 5
6364
; RV64-NEXT: .LBB0_2: # %cond_true
6465
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
65-
; RV64-NEXT: addiw a5, a4, 1
66-
; RV64-NEXT: slli a6, a5, 2
66+
; RV64-NEXT: sw a4, 0(a3)
67+
; RV64-NEXT: addiw a6, a2, 2
68+
; RV64-NEXT: slli a6, a6, 2
6769
; RV64-NEXT: add a6, a0, a6
68-
; RV64-NEXT: sw a2, 0(a6)
69-
; RV64-NEXT: addiw a4, a4, 2
70-
; RV64-NEXT: slli a4, a4, 2
71-
; RV64-NEXT: add a4, a0, a4
72-
; RV64-NEXT: sw a3, 0(a4)
73-
; RV64-NEXT: mv a4, a5
74-
; RV64-NEXT: bne a5, a1, .LBB0_2
70+
; RV64-NEXT: sw a5, 0(a6)
71+
; RV64-NEXT: addiw a2, a2, 1
72+
; RV64-NEXT: addi a3, a3, 4
73+
; RV64-NEXT: bne a1, a2, .LBB0_2
7574
; RV64-NEXT: .LBB0_3: # %return
7675
; RV64-NEXT: ret
7776
entry:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -794,20 +794,20 @@ define void @strided_load_startval_add_with_splat(i8* noalias nocapture %0, i8*
794794
; CHECK-NEXT: # %bb.4:
795795
; CHECK-NEXT: beq a4, a5, .LBB12_7
796796
; CHECK-NEXT: .LBB12_5:
797-
; CHECK-NEXT: slli a2, a3, 2
798-
; CHECK-NEXT: add a2, a2, a3
799-
; CHECK-NEXT: add a1, a1, a2
800-
; CHECK-NEXT: li a2, 1024
797+
; CHECK-NEXT: addiw a2, a3, -1024
798+
; CHECK-NEXT: add a0, a0, a3
799+
; CHECK-NEXT: slli a4, a3, 2
800+
; CHECK-NEXT: add a3, a4, a3
801+
; CHECK-NEXT: add a1, a1, a3
801802
; CHECK-NEXT: .LBB12_6: # =>This Inner Loop Header: Depth=1
802-
; CHECK-NEXT: lb a4, 0(a1)
803-
; CHECK-NEXT: add a5, a0, a3
804-
; CHECK-NEXT: lb a6, 0(a5)
805-
; CHECK-NEXT: addw a4, a6, a4
806-
; CHECK-NEXT: sb a4, 0(a5)
807-
; CHECK-NEXT: addiw a4, a3, 1
808-
; CHECK-NEXT: addi a3, a3, 1
803+
; CHECK-NEXT: lb a3, 0(a1)
804+
; CHECK-NEXT: lb a4, 0(a0)
805+
; CHECK-NEXT: addw a3, a4, a3
806+
; CHECK-NEXT: sb a3, 0(a0)
807+
; CHECK-NEXT: addiw a2, a2, 1
808+
; CHECK-NEXT: addi a0, a0, 1
809809
; CHECK-NEXT: addi a1, a1, 5
810-
; CHECK-NEXT: bne a4, a2, .LBB12_6
810+
; CHECK-NEXT: bnez a2, .LBB12_6
811811
; CHECK-NEXT: .LBB12_7:
812812
; CHECK-NEXT: ret
813813
%4 = icmp eq i32 %2, 1024

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -286,14 +286,12 @@ define dso_local void @splat_load_licm(float* %0) {
286286
; RV64-NEXT: addi a1, a1, %lo(.LCPI12_0)
287287
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
288288
; RV64-NEXT: vlse32.v v8, (a1), zero
289-
; RV64-NEXT: li a1, 0
290-
; RV64-NEXT: li a2, 1024
289+
; RV64-NEXT: li a1, 1024
291290
; RV64-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
292-
; RV64-NEXT: slli a3, a1, 2
293-
; RV64-NEXT: add a3, a0, a3
294-
; RV64-NEXT: addiw a1, a1, 4
295-
; RV64-NEXT: vse32.v v8, (a3)
296-
; RV64-NEXT: bne a1, a2, .LBB12_1
291+
; RV64-NEXT: vse32.v v8, (a0)
292+
; RV64-NEXT: addiw a1, a1, -4
293+
; RV64-NEXT: addi a0, a0, 16
294+
; RV64-NEXT: bnez a1, .LBB12_1
297295
; RV64-NEXT: # %bb.2:
298296
; RV64-NEXT: ret
299297
br label %2

‎llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,11 @@ TEST(DataLayoutUpgradeTest, ValidDataLayoutUpgrade) {
3131
// Check that AMDGPU targets add -G1 if it's not present.
3232
EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32", "r600"), "e-p:32:32-G1");
3333
EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64", "amdgcn"), "e-p:64:64-G1");
34+
35+
// Check that RISCV64 upgrades -n64 to -n32:64.
36+
EXPECT_EQ(UpgradeDataLayoutString("e-m:e-p:64:64-i64:64-i128:128-n64-S128",
37+
"riscv64"),
38+
"e-m:e-p:64:64-i64:64-i128:128-n32:64-S128");
3439
}
3540

3641
TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) {

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