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michaelmaitlandmichaelmaitland
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[RISCV][VLOPT] Add support for more instructions in vl-opt-op-info.mir (#119416)
Specifically, some more where EMUL=LMUL and EEW=SEW.
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-66
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2 files changed

+210
-66
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‎llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll

-66
Original file line numberDiff line numberDiff line change
@@ -2594,71 +2594,6 @@ define <vscale x 4 x i32> @vwsll_vi(<vscale x 4 x i16> %a, <vscale x 4 x i32> %b
25942594
ret <vscale x 4 x i32> %2
25952595
}
25962596

2597-
; Test getOperandInfo
2598-
2599-
define <vscale x 1 x i8> @vmerge_vim(<vscale x 1 x i8> %a, i8 %b, <vscale x 1 x i1> %m, iXLen %vl) {
2600-
; NOVLOPT-LABEL: vmerge_vim:
2601-
; NOVLOPT: # %bb.0:
2602-
; NOVLOPT-NEXT: vsetvli a2, zero, e8, mf8, tu, ma
2603-
; NOVLOPT-NEXT: vmv.v.x v8, a0
2604-
; NOVLOPT-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
2605-
; NOVLOPT-NEXT: vmerge.vim v8, v8, 2, v0
2606-
; NOVLOPT-NEXT: ret
2607-
;
2608-
; VLOPT-LABEL: vmerge_vim:
2609-
; VLOPT: # %bb.0:
2610-
; VLOPT-NEXT: vsetvli zero, a1, e8, mf8, tu, ma
2611-
; VLOPT-NEXT: vmv.v.x v8, a0
2612-
; VLOPT-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
2613-
; VLOPT-NEXT: vmerge.vim v8, v8, 2, v0
2614-
; VLOPT-NEXT: ret
2615-
%2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8(<vscale x 1 x i8> %a, i8 %b, iXLen -1)
2616-
%3 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> %2, i8 2, <vscale x 1 x i1> %m, iXLen %vl)
2617-
ret <vscale x 1 x i8> %3
2618-
}
2619-
2620-
define <vscale x 1 x i8> @vmerge_vxm(<vscale x 1 x i8> %a, i8 %b, <vscale x 1 x i1> %m, iXLen %vl) {
2621-
; NOVLOPT-LABEL: vmerge_vxm:
2622-
; NOVLOPT: # %bb.0:
2623-
; NOVLOPT-NEXT: vsetvli a2, zero, e8, mf8, tu, ma
2624-
; NOVLOPT-NEXT: vmv.v.x v8, a0
2625-
; NOVLOPT-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
2626-
; NOVLOPT-NEXT: vmerge.vxm v8, v8, a0, v0
2627-
; NOVLOPT-NEXT: ret
2628-
;
2629-
; VLOPT-LABEL: vmerge_vxm:
2630-
; VLOPT: # %bb.0:
2631-
; VLOPT-NEXT: vsetvli zero, a1, e8, mf8, tu, ma
2632-
; VLOPT-NEXT: vmv.v.x v8, a0
2633-
; VLOPT-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
2634-
; VLOPT-NEXT: vmerge.vxm v8, v8, a0, v0
2635-
; VLOPT-NEXT: ret
2636-
%2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8(<vscale x 1 x i8> %a, i8 %b, iXLen -1)
2637-
%3 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> %2, i8 %b, <vscale x 1 x i1> %m, iXLen %vl)
2638-
ret <vscale x 1 x i8> %3
2639-
}
2640-
2641-
define <vscale x 1 x i8> @vmerge_vvm(<vscale x 1 x i8> %a, i8 %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, iXLen %vl) {
2642-
; NOVLOPT-LABEL: vmerge_vvm:
2643-
; NOVLOPT: # %bb.0:
2644-
; NOVLOPT-NEXT: vsetvli a2, zero, e8, mf8, tu, ma
2645-
; NOVLOPT-NEXT: vmv.v.x v8, a0
2646-
; NOVLOPT-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
2647-
; NOVLOPT-NEXT: vmerge.vvm v8, v8, v9, v0
2648-
; NOVLOPT-NEXT: ret
2649-
;
2650-
; VLOPT-LABEL: vmerge_vvm:
2651-
; VLOPT: # %bb.0:
2652-
; VLOPT-NEXT: vsetvli zero, a1, e8, mf8, tu, ma
2653-
; VLOPT-NEXT: vmv.v.x v8, a0
2654-
; VLOPT-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
2655-
; VLOPT-NEXT: vmerge.vvm v8, v8, v9, v0
2656-
; VLOPT-NEXT: ret
2657-
%2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8(<vscale x 1 x i8> %a, i8 %b, iXLen -1)
2658-
%3 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> %2, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, iXLen %vl)
2659-
ret <vscale x 1 x i8> %3
2660-
}
2661-
26622597
define <vscale x 1 x i32> @vmand_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {
26632598
; NOVLOPT-LABEL: vmand_mm:
26642599
; NOVLOPT: # %bb.0:
@@ -2950,4 +2885,3 @@ define <vscale x 1 x i32> @vmsof_m(<vscale x 1 x i1> %a, <vscale x 1 x i32> %c,
29502885
%3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)
29512886
ret <vscale x 1 x i32> %3
29522887
}
2953-

‎llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir

+210
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,36 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
22
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s
33

4+
---
5+
name: vop_vi
6+
body: |
7+
bb.0:
8+
; CHECK-LABEL: name: vop_vi
9+
; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, 1, 3 /* e8 */, 0 /* tu, mu */
10+
; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
11+
%x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0
12+
%y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0
13+
...
14+
---
15+
name: vop_vi_incompatible_eew
16+
body: |
17+
bb.0:
18+
; CHECK-LABEL: name: vop_vi_incompatible_eew
19+
; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0 /* tu, mu */
20+
; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
21+
%x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0
22+
%y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0
23+
...
24+
---
25+
name: vop_vi_incompatible_emul
26+
body: |
27+
bb.0:
28+
; CHECK-LABEL: name: vop_vi_incompatible_emul
29+
; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0 /* tu, mu */
30+
; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
31+
%x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0
32+
%y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0
33+
...
434
---
535
name: vop_vv
636
body: |
@@ -682,3 +712,183 @@ body: |
682712
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
683713
%y:vr = PseudoVMSEQ_VV_MF2 $noreg, %x, 1, 3 /* e8 */
684714
...
715+
---
716+
name: vmerge_vim
717+
body: |
718+
bb.0:
719+
; CHECK-LABEL: name: vmerge_vim
720+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
721+
; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */
722+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
723+
%y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */
724+
...
725+
---
726+
name: vmerge_vim_incompatible_eew
727+
body: |
728+
bb.0:
729+
; CHECK-LABEL: name: vmerge_vim_incompatible_eew
730+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
731+
; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */
732+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
733+
%y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */
734+
...
735+
---
736+
name: vmerge_vim_incompatible_emul
737+
body: |
738+
bb.0:
739+
; CHECK-LABEL: name: vmerge_vim_incompatible_emul
740+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
741+
; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_MF2 $noreg, %x, 9, $v0, 1, 3 /* e8 */
742+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
743+
%y:vrnov0 = PseudoVMERGE_VIM_MF2 $noreg, %x, 9, $v0, 1, 3 /* e8 */
744+
...
745+
---
746+
name: vmerge_vxm
747+
body: |
748+
bb.0:
749+
; CHECK-LABEL: name: vmerge_vxm
750+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
751+
; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */
752+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
753+
%y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */
754+
...
755+
---
756+
name: vmerge_vxm_incompatible_eew
757+
body: |
758+
bb.0:
759+
; CHECK-LABEL: name: vmerge_vxm_incompatible_eew
760+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
761+
; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */
762+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
763+
%y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */
764+
...
765+
---
766+
name: vmerge_vxm_incompatible_emul
767+
body: |
768+
bb.0:
769+
; CHECK-LABEL: name: vmerge_vxm_incompatible_emul
770+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
771+
; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VXM_MF2 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */
772+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
773+
%y:vrnov0 = PseudoVMERGE_VXM_MF2 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */
774+
...
775+
---
776+
name: vmerge_vvm
777+
body: |
778+
bb.0:
779+
; CHECK-LABEL: name: vmerge_vvm
780+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
781+
; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */
782+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
783+
%y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */
784+
...
785+
---
786+
name: vmerge_vvm_incompatible_eew
787+
body: |
788+
bb.0:
789+
; CHECK-LABEL: name: vmerge_vvm_incompatible_eew
790+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
791+
; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */
792+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
793+
%y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */
794+
...
795+
---
796+
name: vmerge_vvm_incompatible_emul
797+
body: |
798+
bb.0:
799+
; CHECK-LABEL: name: vmerge_vvm_incompatible_emul
800+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
801+
; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_MF2 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */
802+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
803+
%y:vrnov0 = PseudoVMERGE_VVM_MF2 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */
804+
...
805+
---
806+
name: vmv_v_i
807+
body: |
808+
bb.0:
809+
; CHECK-LABEL: name: vmv_v_i
810+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
811+
; CHECK-NEXT: %y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 3 /* e8 */, 0 /* tu, mu */
812+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
813+
%y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 3 /* e8 */, 0
814+
...
815+
---
816+
name: vmv_v_i_incompatible_eew
817+
body: |
818+
bb.0:
819+
; CHECK-LABEL: name: vmv_v_i_incompatible_eew
820+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
821+
; CHECK-NEXT: %y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 3 /* e8 */, 0 /* tu, mu */
822+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
823+
%y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 3 /* e8 */, 0
824+
...
825+
---
826+
name: vmv_v_i_incompatible_emul
827+
body: |
828+
bb.0:
829+
; CHECK-LABEL: name: vmv_v_i_incompatible_emul
830+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
831+
; CHECK-NEXT: %y:vr = PseudoVMV_V_I_MF2 %x, 9, 1, 3 /* e8 */, 0 /* tu, mu */
832+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
833+
%y:vr = PseudoVMV_V_I_MF2 %x, 9, 1, 3 /* e8 */, 0
834+
...
835+
---
836+
name: vmv_v_x
837+
body: |
838+
bb.0:
839+
; CHECK-LABEL: name: vmv_v_x
840+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
841+
; CHECK-NEXT: %y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
842+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
843+
%y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1, 3 /* e8 */, 0
844+
...
845+
---
846+
name: vmv_v_x_incompatible_eew
847+
body: |
848+
bb.0:
849+
; CHECK-LABEL: name: vmv_v_x_incompatible_eew
850+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
851+
; CHECK-NEXT: %y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
852+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
853+
%y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1, 3 /* e8 */, 0
854+
...
855+
---
856+
name: vmv_v_x_incompatible_emul
857+
body: |
858+
bb.0:
859+
; CHECK-LABEL: name: vmv_v_x_incompatible_emul
860+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
861+
; CHECK-NEXT: %y:vr = PseudoVMV_V_X_MF2 %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
862+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
863+
%y:vr = PseudoVMV_V_X_MF2 %x, $noreg, 1, 3 /* e8 */, 0
864+
...
865+
---
866+
name: vmv_v_v
867+
body: |
868+
bb.0:
869+
; CHECK-LABEL: name: vmv_v_v
870+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
871+
; CHECK-NEXT: %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
872+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
873+
%y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1, 3 /* e8 */, 0
874+
...
875+
---
876+
name: vmv_v_v_incompatible_eew
877+
body: |
878+
bb.0:
879+
; CHECK-LABEL: name: vmv_v_v_incompatible_eew
880+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
881+
; CHECK-NEXT: %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
882+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
883+
%y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1, 3 /* e8 */, 0
884+
...
885+
---
886+
name: vmv_v_v_incompatible_emul
887+
body: |
888+
bb.0:
889+
; CHECK-LABEL: name: vmv_v_v_incompatible_emul
890+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
891+
; CHECK-NEXT: %y:vr = PseudoVMV_V_V_MF2 $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
892+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
893+
%y:vr = PseudoVMV_V_V_MF2 $noreg, %x, 1, 3 /* e8 */, 0
894+
...

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