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Handle Call Operand vxi1 in Hexagon Backend
This commit updates the Hexagon backend to handle vxi1 call operands. It ensures compatibility for vector types of sizes 4, 8, 16, 32, 64, and 128 x i1 when HVX is enabled. Change-Id: I601157c1a5a2258797440f1af88ffd1fde36b9b7
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‎llvm/lib/Target/Hexagon/HexagonCallingConv.td

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Original file line numberDiff line numberDiff line change
@@ -65,6 +65,8 @@ def CC_Hexagon: CallingConv<[
6565
CCIfType<[i32],
6666
CCIfSplit<
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CCCustom<"CC_SkipOdd">>>,
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CCIfType<[v4i1], CCPromoteToType<v4i16>>,
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CCIfType<[v8i1], CCPromoteToType<v8i8>>,
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CCIfType<[i32,v2i16,v4i8],
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CCAssignToReg<[R0,R1,R2,R3,R4,R5]>>,
@@ -111,6 +113,14 @@ class CCIfHvx128<CCAction A>
111113

112114
def CC_Hexagon_HVX: CallingConv<[
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// HVX 64-byte mode
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CCIfHvx64<
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CCIfType<[v16i1], CCPromoteToType<v16i32>>>,
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CCIfHvx64<
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CCIfType<[v32i1], CCPromoteToType<v32i16>>>,
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CCIfHvx64<
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CCIfType<[v64i1], CCPromoteToType<v64i8>>>,
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CCIfHvx64<
115125
CCIfType<[v16i32,v32i16,v64i8],
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CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
@@ -125,6 +135,14 @@ def CC_Hexagon_HVX: CallingConv<[
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CCAssignToStack<128,64>>>,
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// HVX 128-byte mode
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CCIfHvx128<
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CCIfType<[v32i1], CCPromoteToType<v32i32>>>,
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CCIfHvx128<
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CCIfType<[v64i1], CCPromoteToType<v64i16>>>,
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CCIfHvx128<
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CCIfType<[v128i1], CCPromoteToType<v128i8>>>,
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CCIfHvx128<
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CCIfType<[v32i32,v64i16,v128i8,v32f32,v64f16],
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CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,

‎llvm/test/CodeGen/Hexagon/calloperand-v128i1.ll

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@@ -0,0 +1,39 @@
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;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s
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; CHECK-LABEL: compare_vectors
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; CHECK: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
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; CHECK: [[REG2:(r[0-9]+)]] = #-1
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; CHECK: v0 = vand([[REG1]],[[REG2]])
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define void @compare_vectors(<128 x i8> %a, <128 x i8> %b) {
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entry:
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%result = icmp eq <128 x i8> %a, %b
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call i32 @f.1(<128 x i1> %result)
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ret void
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}
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; CHECK-LABEL: f.1:
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; CHECK: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
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; CHECK: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
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; CHECK: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})
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define i32 @f.1(<128 x i1> %vec) {
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%element = extractelement <128 x i1> %vec, i32 6
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%is_true = icmp eq i1 %element, true
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br i1 %is_true, label %if_true, label %if_false
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if_true:
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call void @action_if_true()
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br label %end
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if_false:
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call void @action_if_false()
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br label %end
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end:
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%result = phi i32 [1, %if_true], [0, %if_false]
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ret i32 %result
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}
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declare void @action_if_true()
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declare void @action_if_false()

‎llvm/test/CodeGen/Hexagon/calloperand-v16i1.ll

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@@ -0,0 +1,40 @@
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;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK
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;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK
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; CHECK-LABEL: compare_vectors
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; CHECK: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
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; CHECK: [[REG2:(r[0-9]+)]] = #-1
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; CHECK: v0 = vand([[REG1]],[[REG2]])
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define void @compare_vectors(<16 x i32> %a, <16 x i32> %b) {
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entry:
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%result = icmp eq <16 x i32> %a, %b
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call i32 @f.1(<16 x i1> %result)
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ret void
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}
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; CHECK-LABEL: f.1:
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; CHECK: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
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; CHECK: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
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; CHECK: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})
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define i32 @f.1(<16 x i1> %vec) {
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%element = extractelement <16 x i1> %vec, i32 6
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%is_true = icmp eq i1 %element, true
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br i1 %is_true, label %if_true, label %if_false
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if_true:
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call void @action_if_true()
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br label %end
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if_false:
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call void @action_if_false()
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br label %end
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end:
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%result = phi i32 [1, %if_true], [0, %if_false]
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ret i32 %result
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}
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declare void @action_if_true()
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declare void @action_if_false()

‎llvm/test/CodeGen/Hexagon/calloperand-v32i1.ll

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; RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK-64
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; RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK-128
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; CHECK-LABEL: compare_vectors
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; CHECK-64: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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; CHECK-64: [[REG2:(r[0-9]+)]] = #-1
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; CHECK-64: v0 = vand([[REG1]],[[REG2]])
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; CHECK-128: r{{[0-9]+}}:{{[0-9]+}} = combine(##.LCPI0_0,#-1)
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; CHECK-128: [[REG1:(q[0-9]+)]] = vcmp.eq(v0.h,v1.h)
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; CHECK-128: [[REG2:(v[0-9]+)]] = vand([[REG1]],r{{[0-9]+}})
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; CHECK-128: [[REG3:(v[0-9]+)]] = vmem(r{{[0-9]+}}+#0)
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; CHECK-128: [[REG4:(v[0-9]+)]] = vdelta([[REG2]],[[REG3]])
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; CHECK-128: [[REG5:(q[0-9]+)]] = vand([[REG4]],r{{[0-9]+}})
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; CHECK-128: v0 = vand([[REG5]],r{{[0-9]+}})
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define void @compare_vectors(<32 x i16> %a, <32 x i16> %b) {
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entry:
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%result = icmp eq <32 x i16> %a, %b
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call i32 @f.1(<32 x i1> %result)
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ret void
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}
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; CHECK-LABEL: f.1:
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; CHECK-64: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
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; CHECK-64: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
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; CHECK-64: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})
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; CHECK-128: [[REG6:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
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; CHECK-128: [[REG7:(v[0-9]+)]] = vand([[REG6]],r{{[0-9]+}})
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; CHECK-128: r{{[0-9]+}} = vextract([[REG7]],r{{[0-9]+}})
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define i32 @f.1(<32 x i1> %vec) {
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%element = extractelement <32 x i1> %vec, i32 6
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%is_true = icmp eq i1 %element, true
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br i1 %is_true, label %if_true, label %if_false
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if_true:
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call void @action_if_true()
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br label %end
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if_false:
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call void @action_if_false()
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br label %end
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end:
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%result = phi i32 [1, %if_true], [0, %if_false]
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ret i32 %result
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}
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declare void @action_if_true()
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declare void @action_if_false()

‎llvm/test/CodeGen/Hexagon/calloperand-v4i1.ll

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;RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s --check-prefix=CHECK
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;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK
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;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK
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; CHECK-LABEL: compare_vectors
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; CHECK: [[REG0:(p[0-9]+)]] = vcmph.eq([[REG1:(r[0-9]+):[0-9]]],[[REG2:(r[0-9]+):[0-9]]])
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; CHECK: [[REG1:(r[0-9]+):[0-9]]] = CONST64(#281479271743489)
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; CHECK: [[REG2:(r[0-9]+):[0-9]]] = mask([[REG0]])
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; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and([[REG2]],[[REG1]])
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define void @compare_vectors(<4 x i16> %a, <4 x i16> %b) {
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entry:
13+
%result = icmp eq <4 x i16> %a, %b
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call i32 @f.1(<4 x i1> %result)
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ret void
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}
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; CHECK-LABEL: f.1:
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; CHECK: [[REG3:(r[0-9]+)]] = and([[REG3]],##65537)
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; CHECK: [[REG4:(r[0-9]+)]] = and([[REG4]],##65537)
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define i32 @f.1(<4 x i1> %vec) {
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%element = extractelement <4 x i1> %vec, i32 2
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%is_true = icmp eq i1 %element, true
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br i1 %is_true, label %if_true, label %if_false
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if_true:
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call void @action_if_true()
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br label %end
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if_false:
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call void @action_if_false()
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br label %end
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end:
34+
%result = phi i32 [1, %if_true], [0, %if_false]
35+
ret i32 %result
36+
}
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declare void @action_if_true()
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declare void @action_if_false()

‎llvm/test/CodeGen/Hexagon/calloperand-v64i1.ll

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; RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK-64
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; RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK-128
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; CHECK-LABEL: compare_vectors
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; CHECK-64: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
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; CHECK-64: [[REG2:(r[0-9]+)]] = #-1
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; CHECK-64: v0 = vand([[REG1]],[[REG2]])
8+
; CHECK-128: r{{[0-9]+}}:{{[0-9]+}} = combine(##.LCPI0_0,#-1)
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; CHECK-128: [[REG1:(q[0-9]+)]] = vcmp.eq(v0.b,v1.b)
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; CHECK-128: [[REG2:(v[0-9]+)]] = vand([[REG1]],r{{[0-9]+}})
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; CHECK-128: [[REG3:(v[0-9]+)]] = vmem(r{{[0-9]+}}+#0)
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; CHECK-128: [[REG4:(v[0-9]+)]] = vdelta([[REG2]],[[REG3]])
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; CHECK-128: [[REG5:(q[0-9]+)]] = vand([[REG4]],r{{[0-9]+}})
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; CHECK-128: v0 = vand([[REG5]],r{{[0-9]+}})
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define void @compare_vectors(<64 x i8> %a, <64 x i8> %b) {
17+
entry:
18+
%result = icmp eq <64 x i8> %a, %b
19+
call i32 @f.1(<64 x i1> %result)
20+
ret void
21+
}
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; CHECK-LABEL: f.1:
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; CHECK-64: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
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; CHECK-64: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
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; CHECK-64: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})
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; CHECK-128: [[REG6:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
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; CHECK-128: [[REG7:(v[0-9]+)]] = vand([[REG6]],r{{[0-9]+}})
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; CHECK-128: r{{[0-9]+}} = vextract([[REG7]],r{{[0-9]+}})
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define i32 @f.1(<64 x i1> %vec) {
32+
%element = extractelement <64 x i1> %vec, i32 6
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%is_true = icmp eq i1 %element, true
34+
br i1 %is_true, label %if_true, label %if_false
35+
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if_true:
37+
call void @action_if_true()
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br label %end
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40+
if_false:
41+
call void @action_if_false()
42+
br label %end
43+
44+
end:
45+
%result = phi i32 [1, %if_true], [0, %if_false]
46+
ret i32 %result
47+
}
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declare void @action_if_true()
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declare void @action_if_false()

‎llvm/test/CodeGen/Hexagon/calloperand-v8i1.ll

Lines changed: 39 additions & 0 deletions
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@@ -0,0 +1,39 @@
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;RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s --check-prefix=CHECK
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;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK
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;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK
4+
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; CHECK-LABEL: compare_vectors
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; CHECK: [[REG0:(p[0-9]+)]] = vcmpb.eq([[REG1:(r[0-9]+):[0-9]]],[[REG2:(r[0-9]+):[0-9]]])
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; CHECK: [[REG1:(r[0-9]+):[0-9]]] = CONST64(#72340172838076673)
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; CHECK: [[REG2:(r[0-9]+):[0-9]]] = mask([[REG0]])
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; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and([[REG2]],[[REG1]])
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define void @compare_vectors(<8 x i8> %a, <8 x i8> %b) {
12+
entry:
13+
%result = icmp eq <8 x i8> %a, %b
14+
call i32 @f.1(<8 x i1> %result)
15+
ret void
16+
}
17+
; CHECK-LABEL: f.1:
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; CHECK: [[REG3:(r[0-9]+)]] = and([[REG3]],##16843009)
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; CHECK: [[REG4:(r[0-9]+)]] = and([[REG4]],##16843009)
20+
define i32 @f.1(<8 x i1> %vec) {
21+
%element = extractelement <8 x i1> %vec, i32 6
22+
%is_true = icmp eq i1 %element, true
23+
br i1 %is_true, label %if_true, label %if_false
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if_true:
26+
call void @action_if_true()
27+
br label %end
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if_false:
30+
call void @action_if_false()
31+
br label %end
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33+
end:
34+
%result = phi i32 [1, %if_true], [0, %if_false]
35+
ret i32 %result
36+
}
37+
38+
declare void @action_if_true()
39+
declare void @action_if_false()

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