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farzonlfarzonl
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start of tan intrinsic
copy over X86ISelLowering and x86 test cases from @junaire's https://reviews.llvm.org/D146905 fix test case run clang format fix unit test and documentation
1 parent e1c3e16 commit 8dcbf0d

20 files changed

+350
-10
lines changed

‎llvm/include/llvm/Analysis/VecFuncs.def

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,7 @@ TLI_DEFINE_VECFUNC("llvm.sin.f32", "vsinf", FIXED(4), "_ZGV_LLVM_N4v")
4949
TLI_DEFINE_VECFUNC("cosf", "vcosf", FIXED(4), "_ZGV_LLVM_N4v")
5050
TLI_DEFINE_VECFUNC("llvm.cos.f32", "vcosf", FIXED(4), "_ZGV_LLVM_N4v")
5151
TLI_DEFINE_VECFUNC("tanf", "vtanf", FIXED(4), "_ZGV_LLVM_N4v")
52+
TLI_DEFINE_VECFUNC("llvm.tan.f32", "vtanf", FIXED(4), "_ZGV_LLVM_N4v")
5253
TLI_DEFINE_VECFUNC("asinf", "vasinf", FIXED(4), "_ZGV_LLVM_N4v")
5354
TLI_DEFINE_VECFUNC("acosf", "vacosf", FIXED(4), "_ZGV_LLVM_N4v")
5455
TLI_DEFINE_VECFUNC("atanf", "vatanf", FIXED(4), "_ZGV_LLVM_N4v")

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1973,6 +1973,9 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
19731973
case Intrinsic::cos:
19741974
ISD = ISD::FCOS;
19751975
break;
1976+
case Intrinsic::tan:
1977+
ISD = ISD::FTAN;
1978+
break;
19761979
case Intrinsic::exp:
19771980
ISD = ISD::FEXP;
19781981
break;

‎llvm/include/llvm/IR/RuntimeLibcalls.def

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,11 @@ HANDLE_LIBCALL(COS_F64, "cos")
197197
HANDLE_LIBCALL(COS_F80, "cosl")
198198
HANDLE_LIBCALL(COS_F128, "cosl")
199199
HANDLE_LIBCALL(COS_PPCF128, "cosl")
200+
HANDLE_LIBCALL(TAN_F32, "tanf")
201+
HANDLE_LIBCALL(TAN_F64, "tan")
202+
HANDLE_LIBCALL(TAN_F80, "tanl")
203+
HANDLE_LIBCALL(TAN_F128,"tanl")
204+
HANDLE_LIBCALL(TAN_PPCF128, "tanl")
200205
HANDLE_LIBCALL(SINCOS_F32, nullptr)
201206
HANDLE_LIBCALL(SINCOS_F64, nullptr)
202207
HANDLE_LIBCALL(SINCOS_F80, nullptr)

‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -148,6 +148,7 @@ def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
148148
def : GINodeEquiv<G_FCEIL, fceil>;
149149
def : GINodeEquiv<G_FCOS, fcos>;
150150
def : GINodeEquiv<G_FSIN, fsin>;
151+
def : GINodeEquiv<G_FTAN, ftan>;
151152
def : GINodeEquiv<G_FABS, fabs>;
152153
def : GINodeEquiv<G_FSQRT, fsqrt>;
153154
def : GINodeEquiv<G_FFLOOR, ffloor>;

‎llvm/include/llvm/Target/TargetSelectionDAG.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -509,6 +509,7 @@ def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
509509
def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
510510
def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
511511
def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
512+
def ftan : SDNode<"ISD::FTAN" , SDTFPUnaryOp>;
512513
def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
513514
def fexp10 : SDNode<"ISD::FEXP10" , SDTFPUnaryOp>;
514515
def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
@@ -562,6 +563,8 @@ def strict_fsin : SDNode<"ISD::STRICT_FSIN",
562563
SDTFPUnaryOp, [SDNPHasChain]>;
563564
def strict_fcos : SDNode<"ISD::STRICT_FCOS",
564565
SDTFPUnaryOp, [SDNPHasChain]>;
566+
def strict_ftan : SDNode<"ISD::STRICT_FTAN",
567+
SDTFPUnaryOp, [SDNPHasChain]>;
565568
def strict_fexp2 : SDNode<"ISD::STRICT_FEXP2",
566569
SDTFPUnaryOp, [SDNPHasChain]>;
567570
def strict_fpow : SDNode<"ISD::STRICT_FPOW",
@@ -1517,6 +1520,9 @@ def any_fsin : PatFrags<(ops node:$src),
15171520
def any_fcos : PatFrags<(ops node:$src),
15181521
[(strict_fcos node:$src),
15191522
(fcos node:$src)]>;
1523+
def any_ftan : PatFrags<(ops node:$src),
1524+
[(strict_ftan node:$src),
1525+
(ftan node:$src)]>;
15201526
def any_fexp2 : PatFrags<(ops node:$src),
15211527
[(strict_fexp2 node:$src),
15221528
(fexp2 node:$src)]>;

‎llvm/lib/Analysis/VectorUtils.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,7 @@ bool llvm::isTriviallyVectorizable(Intrinsic::ID ID) {
6868
case Intrinsic::sqrt: // Begin floating-point.
6969
case Intrinsic::sin:
7070
case Intrinsic::cos:
71+
case Intrinsic::tan:
7172
case Intrinsic::exp:
7273
case Intrinsic::exp2:
7374
case Intrinsic::log:

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -449,6 +449,8 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
449449
RTLIBCASE(SIN_F);
450450
case TargetOpcode::G_FCOS:
451451
RTLIBCASE(COS_F);
452+
case TargetOpcode::G_FTAN:
453+
RTLIBCASE(TAN_F);
452454
case TargetOpcode::G_FLOG10:
453455
RTLIBCASE(LOG10_F);
454456
case TargetOpcode::G_FLOG:
@@ -1037,6 +1039,7 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
10371039
case TargetOpcode::G_FREM:
10381040
case TargetOpcode::G_FCOS:
10391041
case TargetOpcode::G_FSIN:
1042+
case TargetOpcode::G_FTAN:
10401043
case TargetOpcode::G_FLOG10:
10411044
case TargetOpcode::G_FLOG:
10421045
case TargetOpcode::G_FLOG2:
@@ -2893,6 +2896,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
28932896
case TargetOpcode::G_FFLOOR:
28942897
case TargetOpcode::G_FCOS:
28952898
case TargetOpcode::G_FSIN:
2899+
case TargetOpcode::G_FTAN:
28962900
case TargetOpcode::G_FLOG10:
28972901
case TargetOpcode::G_FLOG:
28982902
case TargetOpcode::G_FLOG2:
@@ -4659,6 +4663,7 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
46594663
case G_INTRINSIC_TRUNC:
46604664
case G_FCOS:
46614665
case G_FSIN:
4666+
case G_FTAN:
46624667
case G_FSQRT:
46634668
case G_BSWAP:
46644669
case G_BITREVERSE:

‎llvm/lib/CodeGen/GlobalISel/Utils.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -833,6 +833,7 @@ bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
833833
case TargetOpcode::G_FREM:
834834
case TargetOpcode::G_FSIN:
835835
case TargetOpcode::G_FCOS:
836+
case TargetOpcode::G_FTAN:
836837
case TargetOpcode::G_FMA:
837838
case TargetOpcode::G_FMAD:
838839
if (SNaN)
@@ -1713,6 +1714,7 @@ bool llvm::isPreISelGenericFloatingPointOpcode(unsigned Opc) {
17131714
case TargetOpcode::G_FREM:
17141715
case TargetOpcode::G_FRINT:
17151716
case TargetOpcode::G_FSIN:
1717+
case TargetOpcode::G_FTAN:
17161718
case TargetOpcode::G_FSQRT:
17171719
case TargetOpcode::G_FSUB:
17181720
case TargetOpcode::G_INTRINSIC_ROUND:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4514,6 +4514,11 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
45144514
RTLIB::COS_F80, RTLIB::COS_F128,
45154515
RTLIB::COS_PPCF128, Results);
45164516
break;
4517+
case ISD::FTAN:
4518+
case ISD::STRICT_FTAN:
4519+
ExpandFPLibCall(Node, RTLIB::TAN_F32, RTLIB::TAN_F64, RTLIB::TAN_F80,
4520+
RTLIB::TAN_F128, RTLIB::TAN_PPCF128, Results);
4521+
break;
45174522
case ISD::FSINCOS:
45184523
// Expand into sincos libcall.
45194524
ExpandSinCosLibCall(Node, Results);
@@ -5468,6 +5473,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
54685473
case ISD::FSQRT:
54695474
case ISD::FSIN:
54705475
case ISD::FCOS:
5476+
case ISD::FTAN:
54715477
case ISD::FLOG:
54725478
case ISD::FLOG2:
54735479
case ISD::FLOG10:
@@ -5492,6 +5498,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
54925498
case ISD::STRICT_FSQRT:
54935499
case ISD::STRICT_FSIN:
54945500
case ISD::STRICT_FCOS:
5501+
case ISD::STRICT_FTAN:
54955502
case ISD::STRICT_FLOG:
54965503
case ISD::STRICT_FLOG2:
54975504
case ISD::STRICT_FLOG10:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -131,6 +131,8 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
131131
case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break;
132132
case ISD::STRICT_FSUB:
133133
case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
134+
case ISD::STRICT_FTAN:
135+
case ISD::FTAN: R = SoftenFloatRes_FTAN(N); break;
134136
case ISD::STRICT_FTRUNC:
135137
case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break;
136138
case ISD::LOAD: R = SoftenFloatRes_LOAD(N); break;
@@ -774,6 +776,12 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
774776
RTLIB::SUB_PPCF128));
775777
}
776778

779+
SDValue DAGTypeLegalizer::SoftenFloatRes_FTAN(SDNode *N) {
780+
return SoftenFloatRes_Unary(
781+
N, GetFPLibCall(N->getValueType(0), RTLIB::TAN_F32, RTLIB::TAN_F64,
782+
RTLIB::TAN_F80, RTLIB::TAN_F128, RTLIB::TAN_PPCF128));
783+
}
784+
777785
SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) {
778786
return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
779787
RTLIB::TRUNC_F32,
@@ -1399,6 +1407,10 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
13991407
case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break;
14001408
case ISD::STRICT_FSUB:
14011409
case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
1410+
case ISD::STRICT_FTAN:
1411+
case ISD::FTAN:
1412+
ExpandFloatRes_FTAN(N, Lo, Hi);
1413+
break;
14021414
case ISD::STRICT_FTRUNC:
14031415
case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break;
14041416
case ISD::LOAD: ExpandFloatRes_LOAD(N, Lo, Hi); break;
@@ -1768,6 +1780,15 @@ void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo,
17681780
RTLIB::SUB_PPCF128), Lo, Hi);
17691781
}
17701782

1783+
void DAGTypeLegalizer::ExpandFloatRes_FTAN(SDNode *N, SDValue &Lo,
1784+
SDValue &Hi) {
1785+
ExpandFloatRes_Unary(N,
1786+
GetFPLibCall(N->getValueType(0), RTLIB::TAN_F32,
1787+
RTLIB::TAN_F64, RTLIB::TAN_F80,
1788+
RTLIB::TAN_F128, RTLIB::TAN_PPCF128),
1789+
Lo, Hi);
1790+
}
1791+
17711792
void DAGTypeLegalizer::ExpandFloatRes_FTRUNC(SDNode *N,
17721793
SDValue &Lo, SDValue &Hi) {
17731794
ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
@@ -2479,6 +2500,7 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
24792500
case ISD::FSIN:
24802501
case ISD::FSQRT:
24812502
case ISD::FTRUNC:
2503+
case ISD::FTAN:
24822504
case ISD::FCANONICALIZE: R = PromoteFloatRes_UnaryOp(N); break;
24832505

24842506
// Binary FP Operations
@@ -2914,6 +2936,7 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
29142936
case ISD::FSIN:
29152937
case ISD::FSQRT:
29162938
case ISD::FTRUNC:
2939+
case ISD::FTAN:
29172940
case ISD::FCANONICALIZE: R = SoftPromoteHalfRes_UnaryOp(N); break;
29182941

29192942
// Binary FP Operations

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -586,6 +586,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
586586
SDValue SoftenFloatRes_FSIN(SDNode *N);
587587
SDValue SoftenFloatRes_FSQRT(SDNode *N);
588588
SDValue SoftenFloatRes_FSUB(SDNode *N);
589+
SDValue SoftenFloatRes_FTAN(SDNode *N);
589590
SDValue SoftenFloatRes_FTRUNC(SDNode *N);
590591
SDValue SoftenFloatRes_LOAD(SDNode *N);
591592
SDValue SoftenFloatRes_ATOMIC_LOAD(SDNode *N);
@@ -667,6 +668,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
667668
void ExpandFloatRes_FSIN (SDNode *N, SDValue &Lo, SDValue &Hi);
668669
void ExpandFloatRes_FSQRT (SDNode *N, SDValue &Lo, SDValue &Hi);
669670
void ExpandFloatRes_FSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
671+
void ExpandFloatRes_FTAN(SDNode *N, SDValue &Lo, SDValue &Hi);
670672
void ExpandFloatRes_FTRUNC (SDNode *N, SDValue &Lo, SDValue &Hi);
671673
void ExpandFloatRes_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
672674
void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -397,6 +397,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
397397
case ISD::FSQRT:
398398
case ISD::FSIN:
399399
case ISD::FCOS:
400+
case ISD::FTAN:
400401
case ISD::FLDEXP:
401402
case ISD::FPOWI:
402403
case ISD::FPOW:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -108,6 +108,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
108108
case ISD::FROUNDEVEN:
109109
case ISD::FSIN:
110110
case ISD::FSQRT:
111+
case ISD::FTAN:
111112
case ISD::FTRUNC:
112113
case ISD::SIGN_EXTEND:
113114
case ISD::SINT_TO_FP:
@@ -1140,6 +1141,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
11401141
case ISD::VP_FROUNDEVEN:
11411142
case ISD::FSIN:
11421143
case ISD::FSQRT: case ISD::VP_SQRT:
1144+
case ISD::FTAN:
11431145
case ISD::FTRUNC:
11441146
case ISD::VP_FROUNDTOZERO:
11451147
case ISD::SINT_TO_FP:
@@ -4400,6 +4402,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
44004402
case ISD::FROUNDEVEN:
44014403
case ISD::FSIN:
44024404
case ISD::FSQRT:
4405+
case ISD::FTAN:
44034406
case ISD::FTRUNC:
44044407
if (unrollExpandedOp())
44054408
break;

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5349,6 +5349,7 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const
53495349
case ISD::FREM:
53505350
case ISD::FSIN:
53515351
case ISD::FCOS:
5352+
case ISD::FTAN:
53525353
case ISD::FMA:
53535354
case ISD::FMAD: {
53545355
if (SNaN)

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6748,6 +6748,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
67486748
case Intrinsic::fabs:
67496749
case Intrinsic::sin:
67506750
case Intrinsic::cos:
6751+
case Intrinsic::tan:
67516752
case Intrinsic::exp10:
67526753
case Intrinsic::floor:
67536754
case Intrinsic::ceil:
@@ -6765,6 +6766,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
67656766
case Intrinsic::fabs: Opcode = ISD::FABS; break;
67666767
case Intrinsic::sin: Opcode = ISD::FSIN; break;
67676768
case Intrinsic::cos: Opcode = ISD::FCOS; break;
6769+
case Intrinsic::tan: Opcode = ISD::FTAN; break;
67686770
case Intrinsic::exp10: Opcode = ISD::FEXP10; break;
67696771
case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
67706772
case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
@@ -9147,6 +9149,12 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) {
91479149
if (visitUnaryFloatCall(I, ISD::FCOS))
91489150
return;
91499151
break;
9152+
case LibFunc_tan:
9153+
case LibFunc_tanf:
9154+
case LibFunc_tanl:
9155+
if (visitUnaryFloatCall(I, ISD::FTAN))
9156+
return;
9157+
break;
91509158
case LibFunc_sqrt:
91519159
case LibFunc_sqrtf:
91529160
case LibFunc_sqrtl:

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -210,6 +210,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
210210
case ISD::FCOS: return "fcos";
211211
case ISD::STRICT_FCOS: return "strict_fcos";
212212
case ISD::FSINCOS: return "fsincos";
213+
case ISD::FTAN: return "ftan";
214+
case ISD::STRICT_FTAN: return "strict_ftan";
213215
case ISD::FTRUNC: return "ftrunc";
214216
case ISD::STRICT_FTRUNC: return "strict_ftrunc";
215217
case ISD::FFLOOR: return "ffloor";

‎llvm/lib/CodeGen/TargetLoweringBase.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -141,6 +141,7 @@ void TargetLoweringBase::InitLibcalls(const Triple &TT) {
141141
setLibcallName(RTLIB::EXP10_F128, "exp10f128");
142142
setLibcallName(RTLIB::SIN_F128, "sinf128");
143143
setLibcallName(RTLIB::COS_F128, "cosf128");
144+
setLibcallName(RTLIB::TAN_F128, "tanf128");
144145
setLibcallName(RTLIB::SINCOS_F128, "sincosf128");
145146
setLibcallName(RTLIB::POW_F128, "powf128");
146147
setLibcallName(RTLIB::POW_FINITE_F128, "__powf128_finite");
@@ -1015,7 +1016,8 @@ void TargetLoweringBase::initActions() {
10151016
setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP,
10161017
ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR, ISD::FNEARBYINT,
10171018
ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, ISD::LROUND,
1018-
ISD::LLROUND, ISD::LRINT, ISD::LLRINT, ISD::FROUNDEVEN},
1019+
ISD::LLROUND, ISD::LRINT, ISD::LLRINT, ISD::FROUNDEVEN,
1020+
ISD::FTAN},
10191021
{MVT::f32, MVT::f64, MVT::f128}, Expand);
10201022

10211023
// Default ISD::TRAP to expand (which turns it into abort).

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