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Print aliases by default
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8 files changed

+54
-52
lines changed

8 files changed

+54
-52
lines changed

‎llvm/lib/Target/Sparc/SparcInstrAliases.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -467,19 +467,19 @@ def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
467467
let Predicates = [HasV9] in {
468468
// cas [rs1], rs2, rd -> casa [rs1] #ASI_P, rs2, rd
469469
def : InstAlias<"cas [$rs1], $rs2, $rd",
470-
(CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x80), 0>;
470+
(CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x80)>;
471471

472472
// casl [rs1], rs2, rd -> casa [rs1] #ASI_P_L, rs2, rd
473473
def : InstAlias<"casl [$rs1], $rs2, $rd",
474-
(CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x88), 0>;
474+
(CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x88)>;
475475

476476
// casx [rs1], rs2, rd -> casxa [rs1] #ASI_P, rs2, rd
477477
def : InstAlias<"casx [$rs1], $rs2, $rd",
478-
(CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x80), 0>;
478+
(CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x80)>;
479479

480480
// casxl [rs1], rs2, rd -> casxa [rs1] #ASI_P_L, rs2, rd
481481
def : InstAlias<"casxl [$rs1], $rs2, $rd",
482-
(CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x88), 0>;
482+
(CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x88)>;
483483
}
484484

485485
// inc rd -> add rd, 1, rd

‎llvm/test/CodeGen/SPARC/64atomics.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ entry:
1818

1919
; CHECK-LABEL: test_cmpxchg_i64
2020
; CHECK: mov 123, [[R:%[gilo][0-7]]]
21-
; CHECK: casxa [%o1] #ASI_P, %o0, [[R]]
21+
; CHECK: casx [%o1], %o0, [[R]]
2222

2323
define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
2424
entry:
@@ -28,7 +28,7 @@ entry:
2828
}
2929

3030
; CHECK-LABEL: test_swap_i64
31-
; CHECK: casxa [%o1] #ASI_P,
31+
; CHECK: casx [%o1],
3232

3333
define i64 @test_swap_i64(i64 %a, i64* %ptr) {
3434
entry:
@@ -39,7 +39,7 @@ entry:
3939
; CHECK-LABEL: test_load_sub_64
4040
; CHECK: membar
4141
; CHECK: sub
42-
; CHECK: casxa [%o0] #ASI_P
42+
; CHECK: casx [%o0]
4343
; CHECK: membar
4444
define zeroext i64 @test_load_sub_64(i64* %p, i64 zeroext %v) {
4545
entry:
@@ -51,7 +51,7 @@ entry:
5151
; CHECK: membar
5252
; CHECK: cmp
5353
; CHECK: movg %xcc
54-
; CHECK: casxa [%o0] #ASI_P
54+
; CHECK: casx [%o0]
5555
; CHECK: membar
5656
define zeroext i64 @test_load_max_64(i64* %p, i64 zeroext %v) {
5757
entry:

‎llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
2727
; CHECK-NEXT: sll %o4, %o0, %o4
2828
; CHECK-NEXT: and %o5, %o3, %g2
2929
; CHECK-NEXT: or %g2, %o4, %o4
30-
; CHECK-NEXT: casa [%o2] #ASI_P, %o5, %o4
30+
; CHECK-NEXT: cas [%o2], %o5, %o4
3131
; CHECK-NEXT: mov %g0, %g2
3232
; CHECK-NEXT: cmp %o4, %o5
3333
; CHECK-NEXT: move %icc, 1, %g2
@@ -70,7 +70,7 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) {
7070
; CHECK-NEXT: sll %o5, %o0, %o5
7171
; CHECK-NEXT: and %g2, %o4, %g3
7272
; CHECK-NEXT: or %g3, %o5, %o5
73-
; CHECK-NEXT: casa [%o2] #ASI_P, %g2, %o5
73+
; CHECK-NEXT: cas [%o2], %g2, %o5
7474
; CHECK-NEXT: mov %g0, %g3
7575
; CHECK-NEXT: cmp %o5, %g2
7676
; CHECK-NEXT: move %icc, 1, %g3
@@ -98,7 +98,7 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) {
9898
; CHECK-NEXT: add %o2, 1, %o2
9999
; CHECK-NEXT: cmp %o3, %o1
100100
; CHECK-NEXT: movcc %icc, 0, %o2
101-
; CHECK-NEXT: casa [%o0] #ASI_P, %o3, %o2
101+
; CHECK-NEXT: cas [%o0], %o3, %o2
102102
; CHECK-NEXT: mov %g0, %o4
103103
; CHECK-NEXT: cmp %o2, %o3
104104
; CHECK-NEXT: move %icc, 1, %o4
@@ -186,7 +186,7 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) {
186186
; CHECK-NEXT: sll %o5, %o0, %o5
187187
; CHECK-NEXT: and %g2, %o3, %g3
188188
; CHECK-NEXT: or %g3, %o5, %o5
189-
; CHECK-NEXT: casa [%o2] #ASI_P, %g2, %o5
189+
; CHECK-NEXT: cas [%o2], %g2, %o5
190190
; CHECK-NEXT: mov %g0, %g3
191191
; CHECK-NEXT: cmp %o5, %g2
192192
; CHECK-NEXT: move %icc, 1, %g3
@@ -231,7 +231,7 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) {
231231
; CHECK-NEXT: sll %g2, %o0, %g2
232232
; CHECK-NEXT: and %g3, %o4, %g4
233233
; CHECK-NEXT: or %g4, %g2, %g2
234-
; CHECK-NEXT: casa [%o2] #ASI_P, %g3, %g2
234+
; CHECK-NEXT: cas [%o2], %g3, %g2
235235
; CHECK-NEXT: mov %g0, %g4
236236
; CHECK-NEXT: cmp %g2, %g3
237237
; CHECK-NEXT: move %icc, 1, %g4
@@ -261,7 +261,7 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) {
261261
; CHECK-NEXT: movgu %icc, %o1, %o2
262262
; CHECK-NEXT: cmp %o3, 0
263263
; CHECK-NEXT: move %icc, %o1, %o2
264-
; CHECK-NEXT: casa [%o0] #ASI_P, %o3, %o2
264+
; CHECK-NEXT: cas [%o0], %o3, %o2
265265
; CHECK-NEXT: mov %g0, %o4
266266
; CHECK-NEXT: cmp %o2, %o3
267267
; CHECK-NEXT: move %icc, 1, %o4

‎llvm/test/CodeGen/SPARC/atomics.ll

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ entry:
9191
; SPARC: [[LABEL1:\.L.*]]:
9292
; SPARC: or %o5, %o4, %g2
9393
; SPARC: or %o5, %o0, %g3
94-
; SPARC: casa [%o2] #ASI_P, %g3, %g2
94+
; SPARC: cas [%o2], %g3, %g2
9595
; SPARC: mov %g0, %g4
9696
; SPARC: cmp %g2, %g3
9797
; SPARC: move %icc, 1, %g4
@@ -122,7 +122,7 @@ entry:
122122
; SPARC64: [[LABEL1:\.L.*]]:
123123
; SPARC64: or %o5, %o4, %g2
124124
; SPARC64: or %o5, %o0, %g3
125-
; SPARC64: casa [%o2] #ASI_P, %g3, %g2
125+
; SPARC64: cas [%o2], %g3, %g2
126126
; SPARC64: mov %g0, %g4
127127
; SPARC64: cmp %g2, %g3
128128
; SPARC64: move %icc, 1, %g4
@@ -162,7 +162,7 @@ entry:
162162
; SPARC: [[LABEL1:\.L.*]]:
163163
; SPARC: or %o5, %o0, %g2
164164
; SPARC: or %o5, %o4, %g3
165-
; SPARC: casa [%o2] #ASI_P, %g3, %g2
165+
; SPARC: cas [%o2], %g3, %g2
166166
; SPARC: mov %g0, %g4
167167
; SPARC: cmp %g2, %g3
168168
; SPARC: move %icc, 1, %g4
@@ -193,7 +193,7 @@ entry:
193193
; SPARC64: [[LABEL1:\.L.*]]:
194194
; SPARC64: or %o5, %o0, %g2
195195
; SPARC64: or %o5, %o4, %g3
196-
; SPARC64: casa [%o2] #ASI_P, %g3, %g2
196+
; SPARC64: cas [%o2], %g3, %g2
197197
; SPARC64: mov %g0, %g4
198198
; SPARC64: cmp %g2, %g3
199199
; SPARC64: move %icc, 1, %g4
@@ -216,10 +216,10 @@ entry:
216216

217217
; SPARC-LABEL: test_cmpxchg_i32
218218
; SPARC: mov 123, [[R:%[gilo][0-7]]]
219-
; SPARC: casa [%o1] #ASI_P, %o0, [[R]]
219+
; SPARC: cas [%o1], %o0, [[R]]
220220
; SPARC64-LABEL: test_cmpxchg_i32
221221
; SPARC64: mov 123, [[R:%[gilo][0-7]]]
222-
; SPARC64: casa [%o1] #ASI_P, %o0, [[R]]
222+
; SPARC64: cas [%o1], %o0, [[R]]
223223
define i32 @test_cmpxchg_i32(i32 %a, i32* %ptr) {
224224
entry:
225225
%pair = cmpxchg i32* %ptr, i32 %a, i32 123 monotonic monotonic
@@ -267,13 +267,13 @@ entry:
267267
; SPARC: membar
268268
; SPARC: .L{{.*}}:
269269
; SPARC: sub
270-
; SPARC: casa [{{%[gilo][0-7]}}] #ASI_P
270+
; SPARC: cas [{{%[gilo][0-7]}}]
271271
; SPARC: membar
272272
; SPARC64-LABEL: test_load_sub_i8
273273
; SPARC64: membar
274274
; SPARC64: .L{{.*}}:
275275
; SPARC64: sub
276-
; SPARC64: casa [{{%[gilo][0-7]}}] #ASI_P
276+
; SPARC64: cas [{{%[gilo][0-7]}}]
277277
; SPARC64: membar
278278
define zeroext i8 @test_load_sub_i8(i8* %p, i8 zeroext %v) {
279279
entry:
@@ -285,13 +285,13 @@ entry:
285285
; SPARC: membar
286286
; SPARC: .L{{.*}}:
287287
; SPARC: sub
288-
; SPARC: casa [{{%[gilo][0-7]}}] #ASI_P
288+
; SPARC: cas [{{%[gilo][0-7]}}]
289289
; SPARC: membar
290290
; SPARC64-LABEL: test_load_sub_i16
291291
; SPARC64: membar
292292
; SPARC64: .L{{.*}}:
293293
; SPARC64: sub
294-
; SPARC64: casa [{{%[gilo][0-7]}}] #ASI_P
294+
; SPARC64: cas [{{%[gilo][0-7]}}]
295295
; SPARC64: membar
296296
define zeroext i16 @test_load_sub_i16(i16* %p, i16 zeroext %v) {
297297
entry:
@@ -303,13 +303,13 @@ entry:
303303
; SPARC: membar
304304
; SPARC: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
305305
; SPARC: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
306-
; SPARC: casa [%o0] #ASI_P, [[V]], [[V2]]
306+
; SPARC: cas [%o0], [[V]], [[V2]]
307307
; SPARC: membar
308308
; SPARC64-LABEL: test_load_add_i32
309309
; SPARC64: membar
310310
; SPARC64: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
311311
; SPARC64: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
312-
; SPARC64: casa [%o0] #ASI_P, [[V]], [[V2]]
312+
; SPARC64: cas [%o0], [[V]], [[V2]]
313313
; SPARC64: membar
314314
define zeroext i32 @test_load_add_i32(i32* %p, i32 zeroext %v) {
315315
entry:
@@ -320,12 +320,12 @@ entry:
320320
; SPARC-LABEL: test_load_xor_32
321321
; SPARC: membar
322322
; SPARC: xor
323-
; SPARC: casa [%o0] #ASI_P
323+
; SPARC: cas [%o0]
324324
; SPARC: membar
325325
; SPARC64-LABEL: test_load_xor_32
326326
; SPARC64: membar
327327
; SPARC64: xor
328-
; SPARC64: casa [%o0] #ASI_P
328+
; SPARC64: cas [%o0]
329329
; SPARC64: membar
330330
define zeroext i32 @test_load_xor_32(i32* %p, i32 zeroext %v) {
331331
entry:
@@ -337,13 +337,13 @@ entry:
337337
; SPARC: membar
338338
; SPARC: and
339339
; SPARC-NOT: xor
340-
; SPARC: casa [%o0] #ASI_P
340+
; SPARC: cas [%o0]
341341
; SPARC: membar
342342
; SPARC64-LABEL: test_load_and_32
343343
; SPARC64: membar
344344
; SPARC64: and
345345
; SPARC64-NOT: xor
346-
; SPARC64: casa [%o0] #ASI_P
346+
; SPARC64: cas [%o0]
347347
; SPARC64: membar
348348
define zeroext i32 @test_load_and_32(i32* %p, i32 zeroext %v) {
349349
entry:
@@ -355,13 +355,13 @@ entry:
355355
; SPARC: membar
356356
; SPARC: and
357357
; SPARC: xor
358-
; SPARC: casa [%o0] #ASI_P
358+
; SPARC: cas [%o0]
359359
; SPARC: membar
360360
; SPARC64-LABEL: test_load_nand_32
361361
; SPARC64: membar
362362
; SPARC64: and
363363
; SPARC64: xor
364-
; SPARC64: casa [%o0] #ASI_P
364+
; SPARC64: cas [%o0]
365365
; SPARC64: membar
366366
define zeroext i32 @test_load_nand_32(i32* %p, i32 zeroext %v) {
367367
entry:
@@ -373,13 +373,13 @@ entry:
373373
; SPARC: membar
374374
; SPARC: cmp
375375
; SPARC: movleu %icc
376-
; SPARC: casa [%o0] #ASI_P
376+
; SPARC: cas [%o0]
377377
; SPARC: membar
378378
; SPARC64-LABEL: test_load_umin_32
379379
; SPARC64: membar
380380
; SPARC64: cmp
381381
; SPARC64: movleu %icc
382-
; SPARC64: casa [%o0] #ASI_P
382+
; SPARC64: cas [%o0]
383383
; SPARC64: membar
384384
define zeroext i32 @test_load_umin_32(i32* %p, i32 zeroext %v) {
385385
entry:

‎llvm/test/MC/Disassembler/Sparc/sparc-atomics.txt

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux | FileCheck %s
22

3-
# CHECK: casa [%i0] #ASI_P, %l6, %o2
3+
# CHECK: cas [%i0], %l6, %o2
44
0xd5,0xe6,0x10,0x16
55

6-
# CHECK: casa [%i0] #ASI_P_L, %l6, %o2
6+
# CHECK: casl [%i0], %l6, %o2
77
0xd5,0xe6,0x11,0x16
88

99
# CHECK: casa [%i0] 255, %l6, %o2
@@ -12,10 +12,10 @@
1212
# CHECK: casa [%i0] %asi, %l6, %o2
1313
0xd5,0xe6,0x20,0x16
1414

15-
# CHECK: casxa [%i0] #ASI_P, %l6, %o2
15+
# CHECK: casx [%i0], %l6, %o2
1616
0xd5,0xf6,0x10,0x16
1717

18-
# CHECK: casxa [%i0] #ASI_P_L, %l6, %o2
18+
# CHECK: casxl [%i0], %l6, %o2
1919
0xd5,0xf6,0x11,0x16
2020

2121
# CHECK: casxa [%i0] 255, %l6, %o2

‎llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,15 +14,17 @@
1414
0xd5 0xf6 0x03 0x16
1515
# V9: casxa [%i0] #ASI_AIUS_L, %l6, %o2
1616
0xd5 0xf6 0x03 0x36
17-
# V9: casxa [%i0] #ASI_P, %l6, %o2
17+
## casx == casxa #ASI_P
18+
# V9: casx [%i0], %l6, %o2
1819
0xd5 0xf6 0x10 0x16
1920
# V9: casxa [%i0] #ASI_S, %l6, %o2
2021
0xd5 0xf6 0x10 0x36
2122
# V9: casxa [%i0] #ASI_PNF, %l6, %o2
2223
0xd5 0xf6 0x10 0x56
2324
# V9: casxa [%i0] #ASI_SNF, %l6, %o2
2425
0xd5 0xf6 0x10 0x76
25-
# V9: casxa [%i0] #ASI_P_L, %l6, %o2
26+
## casxl == casxa #ASI_L
27+
# V9: casxl [%i0], %l6, %o2
2628
0xd5 0xf6 0x11 0x16
2729
# V9: casxa [%i0] #ASI_S_L, %l6, %o2
2830
0xd5 0xf6 0x11 0x36

‎llvm/test/MC/Sparc/sparc-cas-instructions.s

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3,22 +3,22 @@
33
! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
44

55
! V8: error: instruction requires a CPU feature not currently enabled
6-
! V9: casa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
6+
! V9: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
77
! LEON: error: instruction requires a CPU feature not currently enabled
88
cas [%i0], %l6, %o2
99

1010
! V8: error: instruction requires a CPU feature not currently enabled
11-
! V9: casa [%i0] #ASI_P_L, %l6, %o2 ! encoding: [0xd5,0xe6,0x11,0x16]
11+
! V9: casl [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x11,0x16]
1212
! LEON: error: instruction requires a CPU feature not currently enabled
1313
casl [%i0], %l6, %o2
1414

1515
! V8: error: instruction requires a CPU feature not currently enabled
16-
! V9: casxa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
16+
! V9: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
1717
! LEON: error: instruction requires a CPU feature not currently enabled
1818
casx [%i0], %l6, %o2
1919

2020
! V8: error: instruction requires a CPU feature not currently enabled
21-
! V9: casxa [%i0] #ASI_P_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
21+
! V9: casxl [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
2222
! LEON: error: instruction requires a CPU feature not currently enabled
2323
casxl [%i0], %l6, %o2
2424

@@ -28,12 +28,12 @@ casxl [%i0], %l6, %o2
2828
casxa [%i0] %asi, %l6, %o2
2929

3030
! V8: error: instruction requires a CPU feature not currently enabled
31-
! V9: casxa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
31+
! V9: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
3232
! LEON: error: instruction requires a CPU feature not currently enabled
3333
casxa [%i0] 0x80, %l6, %o2
3434

3535
! V8: error: instruction requires a CPU feature not currently enabled
36-
! V9: casxa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
36+
! V9: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
3737
! LEON: error: instruction requires a CPU feature not currently enabled
3838
casxa [%i0] (0x40+0x40), %l6, %o2
3939

@@ -43,11 +43,11 @@ casxa [%i0] (0x40+0x40), %l6, %o2
4343
casa [%i0] %asi, %l6, %o2
4444

4545
! V8: error: instruction requires a CPU feature not currently enabled
46-
! V9: casa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
46+
! V9: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
4747
! LEON: casa [%i0] 128, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
4848
casa [%i0] 0x80, %l6, %o2
4949

5050
! V8: error: instruction requires a CPU feature not currently enabled
51-
! V9: casa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
51+
! V9: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
5252
! LEON: casa [%i0] 128, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
5353
casa [%i0] (0x40+0x40), %l6, %o2

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