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hdelanhdelan
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Remove unneeded declarations in test
Intrinsics are defined with a bfloat type as of commit 250f2bb, not i16 and i32 storage types. As such declarations are no longer needed once the correct types are used.
1 parent e7630a0 commit 88b4b49

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+72
-126
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2 files changed

+72
-126
lines changed

‎llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-autoupgrade.ll

Lines changed: 48 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -1,56 +1,36 @@
11
; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 -mattr=+ptx70 | FileCheck %s
22
; RUN: %if ptxas-11.0 %{ llc < %s -march=nvptx64 -mcpu=sm_80 -mattr=+ptx70 | %ptxas-verify -arch=sm_80 %}
33

4-
declare i16 @llvm.nvvm.abs.bf16(i16)
5-
declare i32 @llvm.nvvm.abs.bf16x2(i32)
6-
declare i16 @llvm.nvvm.neg.bf16(i16)
7-
declare i32 @llvm.nvvm.neg.bf16x2(i32)
8-
9-
declare i16 @llvm.nvvm.fmin.bf16(i16, i16)
10-
declare i16 @llvm.nvvm.fmin.nan.bf16(i16, i16)
11-
declare i32 @llvm.nvvm.fmin.bf16x2(i32, i32)
12-
declare i32 @llvm.nvvm.fmin.nan.bf16x2(i32, i32)
13-
14-
declare i16 @llvm.nvvm.fmax.bf16(i16, i16)
15-
declare i16 @llvm.nvvm.fmax.nan.bf16(i16, i16)
16-
declare i32 @llvm.nvvm.fmax.bf16x2(i32, i32)
17-
declare i32 @llvm.nvvm.fmax.nan.bf16x2(i32, i32)
18-
19-
declare i16 @llvm.nvvm.fma.rn.bf16(i16, i16, i16)
20-
declare i16 @llvm.nvvm.fma.rn.relu.bf16(i16, i16, i16)
21-
declare i32 @llvm.nvvm.fma.rn.bf16x2(i32, i32, i32)
22-
declare i32 @llvm.nvvm.fma.rn.relu.bf16x2(i32, i32, i32)
23-
244
; CHECK-LABEL: abs_bf16
25-
define i16 @abs_bf16(i16 %0) {
5+
define bfloat @abs_bf16(bfloat %0) {
266
; CHECK-NOT: call
277
; CHECK: abs.bf16
28-
%res = call i16 @llvm.nvvm.abs.bf16(i16 %0);
29-
ret i16 %res
8+
%res = call bfloat @llvm.nvvm.abs.bf16(bfloat %0);
9+
ret bfloat %res
3010
}
3111

3212
; CHECK-LABEL: abs_bf16x2
33-
define i32 @abs_bf16x2(i32 %0) {
13+
define <2 x bfloat> @abs_bf16x2(<2 x bfloat> %0) {
3414
; CHECK-NOT: call
3515
; CHECK: abs.bf16x2
36-
%res = call i32 @llvm.nvvm.abs.bf16x2(i32 %0);
37-
ret i32 %res
16+
%res = call <2 x bfloat> @llvm.nvvm.abs.bf16x2(<2 x bfloat> %0);
17+
ret <2 x bfloat> %res
3818
}
3919

4020
; CHECK-LABEL: neg_bf16
41-
define i16 @neg_bf16(i16 %0) {
21+
define bfloat @neg_bf16(bfloat %0) {
4222
; CHECK-NOT: call
4323
; CHECK: neg.bf16
44-
%res = call i16 @llvm.nvvm.neg.bf16(i16 %0);
45-
ret i16 %res
24+
%res = call bfloat @llvm.nvvm.neg.bf16(bfloat %0);
25+
ret bfloat %res
4626
}
4727

4828
; CHECK-LABEL: neg_bf16x2
49-
define i32 @neg_bf16x2(i32 %0) {
29+
define <2 x bfloat> @neg_bf16x2(<2 x bfloat> %0) {
5030
; CHECK-NOT: call
5131
; CHECK: neg.bf16x2
52-
%res = call i32 @llvm.nvvm.neg.bf16x2(i32 %0);
53-
ret i32 %res
32+
%res = call <2 x bfloat> @llvm.nvvm.neg.bf16x2(<2 x bfloat> %0);
33+
ret <2 x bfloat> %res
5434
}
5535

5636
; CHECK-LABEL: fmin_nan_f
@@ -134,35 +114,35 @@ define <2 x half> @fmin_ftz_nan_f16x2(<2 x half> %0, <2 x half> %1) {
134114
}
135115

136116
; CHECK-LABEL: fmin_bf16
137-
define i16 @fmin_bf16(i16 %0, i16 %1) {
117+
define bfloat @fmin_bf16(bfloat %0, bfloat %1) {
138118
; CHECK-NOT: call
139119
; CHECK: min.bf16
140-
%res = call i16 @llvm.nvvm.fmin.bf16(i16 %0, i16 %1)
141-
ret i16 %res
120+
%res = call bfloat @llvm.nvvm.fmin.bf16(bfloat %0, bfloat %1)
121+
ret bfloat %res
142122
}
143123

144124
; CHECK-LABEL: fmin_nan_bf16
145-
define i16 @fmin_nan_bf16(i16 %0, i16 %1) {
125+
define bfloat @fmin_nan_bf16(bfloat %0, bfloat %1) {
146126
; CHECK-NOT: call
147127
; CHECK: min.NaN.bf16
148-
%res = call i16 @llvm.nvvm.fmin.nan.bf16(i16 %0, i16 %1)
149-
ret i16 %res
128+
%res = call bfloat @llvm.nvvm.fmin.nan.bf16(bfloat %0, bfloat %1)
129+
ret bfloat %res
150130
}
151131

152132
; CHECK-LABEL: fmin_bf16x2
153-
define i32 @fmin_bf16x2(i32 %0, i32 %1) {
133+
define <2 x bfloat> @fmin_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
154134
; CHECK-NOT: call
155135
; CHECK: min.bf16x2
156-
%res = call i32 @llvm.nvvm.fmin.bf16x2(i32 %0, i32 %1)
157-
ret i32 %res
136+
%res = call <2 x bfloat> @llvm.nvvm.fmin.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
137+
ret <2 x bfloat> %res
158138
}
159139

160140
; CHECK-LABEL: fmin_nan_bf16x2
161-
define i32 @fmin_nan_bf16x2(i32 %0, i32 %1) {
141+
define <2 x bfloat> @fmin_nan_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
162142
; CHECK-NOT: call
163143
; CHECK: min.NaN.bf16x2
164-
%res = call i32 @llvm.nvvm.fmin.nan.bf16x2(i32 %0, i32 %1)
165-
ret i32 %res
144+
%res = call <2 x bfloat> @llvm.nvvm.fmin.nan.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
145+
ret <2 x bfloat> %res
166146
}
167147

168148
; CHECK-LABEL: fmax_nan_f
@@ -246,35 +226,35 @@ define <2 x half> @fmax_ftz_nan_f16x2(<2 x half> %0, <2 x half> %1) {
246226
}
247227

248228
; CHECK-LABEL: fmax_bf16
249-
define i16 @fmax_bf16(i16 %0, i16 %1) {
229+
define bfloat @fmax_bf16(bfloat %0, bfloat %1) {
250230
; CHECK-NOT: call
251231
; CHECK: max.bf16
252-
%res = call i16 @llvm.nvvm.fmax.bf16(i16 %0, i16 %1)
253-
ret i16 %res
232+
%res = call bfloat @llvm.nvvm.fmax.bf16(bfloat %0, bfloat %1)
233+
ret bfloat %res
254234
}
255235

256236
; CHECK-LABEL: fmax_nan_bf16
257-
define i16 @fmax_nan_bf16(i16 %0, i16 %1) {
237+
define bfloat @fmax_nan_bf16(bfloat %0, bfloat %1) {
258238
; CHECK-NOT: call
259239
; CHECK: max.NaN.bf16
260-
%res = call i16 @llvm.nvvm.fmax.nan.bf16(i16 %0, i16 %1)
261-
ret i16 %res
240+
%res = call bfloat @llvm.nvvm.fmax.nan.bf16(bfloat %0, bfloat %1)
241+
ret bfloat %res
262242
}
263243

264244
; CHECK-LABEL: fmax_bf16x2
265-
define i32 @fmax_bf16x2(i32 %0, i32 %1) {
245+
define <2 x bfloat> @fmax_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
266246
; CHECK-NOT: call
267247
; CHECK: max.bf16x2
268-
%res = call i32 @llvm.nvvm.fmax.bf16x2(i32 %0, i32 %1)
269-
ret i32 %res
248+
%res = call <2 x bfloat> @llvm.nvvm.fmax.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
249+
ret <2 x bfloat> %res
270250
}
271251

272252
; CHECK-LABEL: fmax_nan_bf16x2
273-
define i32 @fmax_nan_bf16x2(i32 %0, i32 %1) {
253+
define <2 x bfloat> @fmax_nan_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
274254
; CHECK-NOT: call
275255
; CHECK: max.NaN.bf16x2
276-
%res = call i32 @llvm.nvvm.fmax.nan.bf16x2(i32 %0, i32 %1)
277-
ret i32 %res
256+
%res = call <2 x bfloat> @llvm.nvvm.fmax.nan.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
257+
ret <2 x bfloat> %res
278258
}
279259

280260
; CHECK-LABEL: fma_rn_relu_f16
@@ -310,33 +290,33 @@ define <2 x half> @fma_rn_ftz_relu_f16x2(<2 x half> %0, <2 x half> %1, <2 x half
310290
}
311291

312292
; CHECK-LABEL: fma_rn_bf16
313-
define i16 @fma_rn_bf16(i16 %0, i16 %1, i16 %2) {
293+
define bfloat @fma_rn_bf16(bfloat %0, bfloat %1, bfloat %2) {
314294
; CHECK-NOT: call
315295
; CHECK: fma.rn.bf16
316-
%res = call i16 @llvm.nvvm.fma.rn.bf16(i16 %0, i16 %1, i16 %2)
317-
ret i16 %res
296+
%res = call bfloat @llvm.nvvm.fma.rn.bf16(bfloat %0, bfloat %1, bfloat %2)
297+
ret bfloat %res
318298
}
319299

320300
; CHECK-LABEL: fma_rn_relu_bf16
321-
define i16 @fma_rn_relu_bf16(i16 %0, i16 %1, i16 %2) {
301+
define bfloat @fma_rn_relu_bf16(bfloat %0, bfloat %1, bfloat %2) {
322302
; CHECK-NOT: call
323303
; CHECK: fma.rn.relu.bf16
324-
%res = call i16 @llvm.nvvm.fma.rn.relu.bf16(i16 %0, i16 %1, i16 %2)
325-
ret i16 %res
304+
%res = call bfloat @llvm.nvvm.fma.rn.relu.bf16(bfloat %0, bfloat %1, bfloat %2)
305+
ret bfloat %res
326306
}
327307

328308
; CHECK-LABEL: fma_rn_bf16x2
329-
define i32 @fma_rn_bf16x2(i32 %0, i32 %1, i32 %2) {
309+
define <2 x bfloat> @fma_rn_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1, <2 x bfloat> %2) {
330310
; CHECK-NOT: call
331311
; CHECK: fma.rn.bf16x2
332-
%res = call i32 @llvm.nvvm.fma.rn.bf16x2(i32 %0, i32 %1, i32 %2)
333-
ret i32 %res
312+
%res = call <2 x bfloat> @llvm.nvvm.fma.rn.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1, <2 x bfloat> %2)
313+
ret <2 x bfloat> %res
334314
}
335315

336316
; CHECK-LABEL: fma_rn_relu_bf16x2
337-
define i32 @fma_rn_relu_bf16x2(i32 %0, i32 %1, i32 %2) {
317+
define <2 x bfloat> @fma_rn_relu_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1, <2 x bfloat> %2) {
338318
; CHECK-NOT: call
339319
; CHECK: fma.rn.relu.bf16x2
340-
%res = call i32 @llvm.nvvm.fma.rn.relu.bf16x2(i32 %0, i32 %1, i32 %2)
341-
ret i32 %res
320+
%res = call <2 x bfloat> @llvm.nvvm.fma.rn.relu.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1, <2 x bfloat> %2)
321+
ret <2 x bfloat> %res
342322
}

‎llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72-autoupgrade.ll

Lines changed: 24 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -1,40 +1,6 @@
11
; RUN: llc < %s -march=nvptx64 -mcpu=sm_86 -mattr=+ptx72 | FileCheck %s
22
; RUN: %if ptxas-11.2 %{ llc < %s -march=nvptx64 -mcpu=sm_86 -mattr=+ptx72 | %ptxas-verify -arch=sm_86 %}
33

4-
declare half @llvm.nvvm.fmin.xorsign.abs.f16(half, half)
5-
declare half @llvm.nvvm.fmin.ftz.xorsign.abs.f16(half, half)
6-
declare half @llvm.nvvm.fmin.nan.xorsign.abs.f16(half, half)
7-
declare half @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16(half, half)
8-
declare <2 x half> @llvm.nvvm.fmin.xorsign.abs.f16x2(<2 x half> , <2 x half>)
9-
declare <2 x half> @llvm.nvvm.fmin.ftz.xorsign.abs.f16x2(<2 x half> , <2 x half>)
10-
declare <2 x half> @llvm.nvvm.fmin.nan.xorsign.abs.f16x2(<2 x half> , <2 x half>)
11-
declare <2 x half> @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16x2(<2 x half> , <2 x half>)
12-
declare i16 @llvm.nvvm.fmin.xorsign.abs.bf16(i16, i16)
13-
declare i16 @llvm.nvvm.fmin.nan.xorsign.abs.bf16(i16, i16)
14-
declare i32 @llvm.nvvm.fmin.xorsign.abs.bf16x2(i32, i32)
15-
declare i32 @llvm.nvvm.fmin.nan.xorsign.abs.bf16x2(i32, i32)
16-
declare float @llvm.nvvm.fmin.xorsign.abs.f(float, float)
17-
declare float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float, float)
18-
declare float @llvm.nvvm.fmin.nan.xorsign.abs.f(float, float)
19-
declare float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float, float)
20-
21-
declare half @llvm.nvvm.fmax.xorsign.abs.f16(half, half)
22-
declare half @llvm.nvvm.fmax.ftz.xorsign.abs.f16(half, half)
23-
declare half @llvm.nvvm.fmax.nan.xorsign.abs.f16(half, half)
24-
declare half @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16(half, half)
25-
declare <2 x half> @llvm.nvvm.fmax.xorsign.abs.f16x2(<2 x half> , <2 x half>)
26-
declare <2 x half> @llvm.nvvm.fmax.ftz.xorsign.abs.f16x2(<2 x half> , <2 x half>)
27-
declare <2 x half> @llvm.nvvm.fmax.nan.xorsign.abs.f16x2(<2 x half> , <2 x half>)
28-
declare <2 x half> @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16x2(<2 x half> , <2 x half>)
29-
declare i16 @llvm.nvvm.fmax.xorsign.abs.bf16(i16, i16)
30-
declare i16 @llvm.nvvm.fmax.nan.xorsign.abs.bf16(i16, i16)
31-
declare i32 @llvm.nvvm.fmax.xorsign.abs.bf16x2(i32, i32)
32-
declare i32 @llvm.nvvm.fmax.nan.xorsign.abs.bf16x2(i32, i32)
33-
declare float @llvm.nvvm.fmax.xorsign.abs.f(float, float)
34-
declare float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float, float)
35-
declare float @llvm.nvvm.fmax.nan.xorsign.abs.f(float, float)
36-
declare float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float, float)
37-
384
; CHECK-LABEL: fmin_xorsign_abs_f16
395
define half @fmin_xorsign_abs_f16(half %0, half %1) {
406
; CHECK-NOT: call
@@ -100,35 +66,35 @@ define <2 x half> @fmin_ftz_nan_xorsign_abs_f16x2(<2 x half> %0, <2 x half> %1)
10066
}
10167

10268
; CHECK-LABEL: fmin_xorsign_abs_bf16
103-
define i16 @fmin_xorsign_abs_bf16(i16 %0, i16 %1) {
69+
define bfloat @fmin_xorsign_abs_bf16(bfloat %0, bfloat %1) {
10470
; CHECK-NOT: call
10571
; CHECK: min.xorsign.abs.bf16
106-
%res = call i16 @llvm.nvvm.fmin.xorsign.abs.bf16(i16 %0, i16 %1)
107-
ret i16 %res
72+
%res = call bfloat @llvm.nvvm.fmin.xorsign.abs.bf16(bfloat %0, bfloat %1)
73+
ret bfloat %res
10874
}
10975

11076
; CHECK-LABEL: fmin_nan_xorsign_abs_bf16
111-
define i16 @fmin_nan_xorsign_abs_bf16(i16 %0, i16 %1) {
77+
define bfloat @fmin_nan_xorsign_abs_bf16(bfloat %0, bfloat %1) {
11278
; CHECK-NOT: call
11379
; CHECK: min.NaN.xorsign.abs.bf16
114-
%res = call i16 @llvm.nvvm.fmin.nan.xorsign.abs.bf16(i16 %0, i16 %1)
115-
ret i16 %res
80+
%res = call bfloat @llvm.nvvm.fmin.nan.xorsign.abs.bf16(bfloat %0, bfloat %1)
81+
ret bfloat %res
11682
}
11783

11884
; CHECK-LABEL: fmin_xorsign_abs_bf16x2
119-
define i32 @fmin_xorsign_abs_bf16x2(i32 %0, i32 %1) {
85+
define <2 x bfloat> @fmin_xorsign_abs_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
12086
; CHECK-NOT: call
12187
; CHECK: min.xorsign.abs.bf16x2
122-
%res = call i32 @llvm.nvvm.fmin.xorsign.abs.bf16x2(i32 %0, i32 %1)
123-
ret i32 %res
88+
%res = call <2 x bfloat> @llvm.nvvm.fmin.xorsign.abs.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
89+
ret <2 x bfloat> %res
12490
}
12591

12692
; CHECK-LABEL: fmin_nan_xorsign_abs_bf16x2
127-
define i32 @fmin_nan_xorsign_abs_bf16x2(i32 %0, i32 %1) {
93+
define <2 x bfloat> @fmin_nan_xorsign_abs_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
12894
; CHECK-NOT: call
12995
; CHECK: min.NaN.xorsign.abs.bf16x2
130-
%res = call i32 @llvm.nvvm.fmin.nan.xorsign.abs.bf16x2(i32 %0, i32 %1)
131-
ret i32 %res
96+
%res = call <2 x bfloat> @llvm.nvvm.fmin.nan.xorsign.abs.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
97+
ret <2 x bfloat> %res
13298
}
13399

134100
; CHECK-LABEL: fmin_xorsign_abs_f
@@ -228,35 +194,35 @@ define <2 x half> @fmax_ftz_nan_xorsign_abs_f16x2(<2 x half> %0, <2 x half> %1)
228194
}
229195

230196
; CHECK-LABEL: fmax_xorsign_abs_bf16
231-
define i16 @fmax_xorsign_abs_bf16(i16 %0, i16 %1) {
197+
define bfloat @fmax_xorsign_abs_bf16(bfloat %0, bfloat %1) {
232198
; CHECK-NOT: call
233199
; CHECK: max.xorsign.abs.bf16
234-
%res = call i16 @llvm.nvvm.fmax.xorsign.abs.bf16(i16 %0, i16 %1)
235-
ret i16 %res
200+
%res = call bfloat @llvm.nvvm.fmax.xorsign.abs.bf16(bfloat %0, bfloat %1)
201+
ret bfloat %res
236202
}
237203

238204
; CHECK-LABEL: fmax_nan_xorsign_abs_bf16
239-
define i16 @fmax_nan_xorsign_abs_bf16(i16 %0, i16 %1) {
205+
define bfloat @fmax_nan_xorsign_abs_bf16(bfloat %0, bfloat %1) {
240206
; CHECK-NOT: call
241207
; CHECK: max.NaN.xorsign.abs.bf16
242-
%res = call i16 @llvm.nvvm.fmax.nan.xorsign.abs.bf16(i16 %0, i16 %1)
243-
ret i16 %res
208+
%res = call bfloat @llvm.nvvm.fmax.nan.xorsign.abs.bf16(bfloat %0, bfloat %1)
209+
ret bfloat %res
244210
}
245211

246212
; CHECK-LABEL: fmax_xorsign_abs_bf16x2
247-
define i32 @fmax_xorsign_abs_bf16x2(i32 %0, i32 %1) {
213+
define <2 x bfloat> @fmax_xorsign_abs_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
248214
; CHECK-NOT: call
249215
; CHECK: max.xorsign.abs.bf16x2
250-
%res = call i32 @llvm.nvvm.fmax.xorsign.abs.bf16x2(i32 %0, i32 %1)
251-
ret i32 %res
216+
%res = call <2 x bfloat> @llvm.nvvm.fmax.xorsign.abs.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
217+
ret <2 x bfloat> %res
252218
}
253219

254220
; CHECK-LABEL: fmax_nan_xorsign_abs_bf16x2
255-
define i32 @fmax_nan_xorsign_abs_bf16x2(i32 %0, i32 %1) {
221+
define <2 x bfloat> @fmax_nan_xorsign_abs_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
256222
; CHECK-NOT: call
257223
; CHECK: max.NaN.xorsign.abs.bf16x2
258-
%res = call i32 @llvm.nvvm.fmax.nan.xorsign.abs.bf16x2(i32 %0, i32 %1)
259-
ret i32 %res
224+
%res = call <2 x bfloat> @llvm.nvvm.fmax.nan.xorsign.abs.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
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ret <2 x bfloat> %res
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}
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; CHECK-LABEL: fmax_xorsign_abs_f

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