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[RISCV] Move RISCVVType namespace to TargetParser (#83222)
Clang and some middle-end optimizations may need these helper functions. This can reduce some duplications.
1 parent 49ec8b7 commit 85388a0

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8 files changed

+173
-165
lines changed

8 files changed

+173
-165
lines changed

‎llvm/include/llvm/TargetParser/RISCVTargetParser.h‎

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@
1515
#define LLVM_TARGETPARSER_RISCVTARGETPARSER_H
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1717
#include "llvm/ADT/StringRef.h"
18+
#include "llvm/Support/MathExtras.h"
19+
#include "llvm/Support/raw_ostream.h"
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1921
namespace llvm {
2022

@@ -36,6 +38,81 @@ void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
3638
bool hasFastUnalignedAccess(StringRef CPU);
3739

3840
} // namespace RISCV
41+
42+
namespace RISCVII {
43+
enum VLMUL : uint8_t {
44+
LMUL_1 = 0,
45+
LMUL_2,
46+
LMUL_4,
47+
LMUL_8,
48+
LMUL_RESERVED,
49+
LMUL_F8,
50+
LMUL_F4,
51+
LMUL_F2
52+
};
53+
54+
enum {
55+
TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
56+
TAIL_AGNOSTIC = 1,
57+
MASK_AGNOSTIC = 2,
58+
};
59+
} // namespace RISCVII
60+
61+
namespace RISCVVType {
62+
// Is this a SEW value that can be encoded into the VTYPE format.
63+
inline static bool isValidSEW(unsigned SEW) {
64+
return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
65+
}
66+
67+
// Is this a LMUL value that can be encoded into the VTYPE format.
68+
inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
69+
return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
70+
}
71+
72+
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
73+
bool MaskAgnostic);
74+
75+
inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
76+
unsigned VLMUL = VType & 0x7;
77+
return static_cast<RISCVII::VLMUL>(VLMUL);
78+
}
79+
80+
// Decode VLMUL into 1,2,4,8 and fractional indicator.
81+
std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
82+
83+
inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
84+
assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
85+
unsigned LmulLog2 = Log2_32(LMUL);
86+
return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
87+
}
88+
89+
inline static unsigned decodeVSEW(unsigned VSEW) {
90+
assert(VSEW < 8 && "Unexpected VSEW value");
91+
return 1 << (VSEW + 3);
92+
}
93+
94+
inline static unsigned encodeSEW(unsigned SEW) {
95+
assert(isValidSEW(SEW) && "Unexpected SEW value");
96+
return Log2_32(SEW) - 3;
97+
}
98+
99+
inline static unsigned getSEW(unsigned VType) {
100+
unsigned VSEW = (VType >> 3) & 0x7;
101+
return decodeVSEW(VSEW);
102+
}
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104+
inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
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inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
107+
108+
void printVType(unsigned VType, raw_ostream &OS);
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unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
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std::optional<RISCVII::VLMUL>
113+
getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
114+
} // namespace RISCVVType
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39116
} // namespace llvm
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#endif

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp‎

Lines changed: 0 additions & 87 deletions
Original file line numberDiff line numberDiff line change
@@ -134,93 +134,6 @@ parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
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135135
} // namespace RISCVFeatures
136136

137-
// Encode VTYPE into the binary format used by the the VSETVLI instruction which
138-
// is used by our MC layer representation.
139-
//
140-
// Bits | Name | Description
141-
// -----+------------+------------------------------------------------
142-
// 7 | vma | Vector mask agnostic
143-
// 6 | vta | Vector tail agnostic
144-
// 5:3 | vsew[2:0] | Standard element width (SEW) setting
145-
// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
146-
unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW,
147-
bool TailAgnostic, bool MaskAgnostic) {
148-
assert(isValidSEW(SEW) && "Invalid SEW");
149-
unsigned VLMULBits = static_cast<unsigned>(VLMUL);
150-
unsigned VSEWBits = encodeSEW(SEW);
151-
unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
152-
if (TailAgnostic)
153-
VTypeI |= 0x40;
154-
if (MaskAgnostic)
155-
VTypeI |= 0x80;
156-
157-
return VTypeI;
158-
}
159-
160-
std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) {
161-
switch (VLMUL) {
162-
default:
163-
llvm_unreachable("Unexpected LMUL value!");
164-
case RISCVII::VLMUL::LMUL_1:
165-
case RISCVII::VLMUL::LMUL_2:
166-
case RISCVII::VLMUL::LMUL_4:
167-
case RISCVII::VLMUL::LMUL_8:
168-
return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
169-
case RISCVII::VLMUL::LMUL_F2:
170-
case RISCVII::VLMUL::LMUL_F4:
171-
case RISCVII::VLMUL::LMUL_F8:
172-
return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
173-
}
174-
}
175-
176-
void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
177-
unsigned Sew = getSEW(VType);
178-
OS << "e" << Sew;
179-
180-
unsigned LMul;
181-
bool Fractional;
182-
std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
183-
184-
if (Fractional)
185-
OS << ", mf";
186-
else
187-
OS << ", m";
188-
OS << LMul;
189-
190-
if (isTailAgnostic(VType))
191-
OS << ", ta";
192-
else
193-
OS << ", tu";
194-
195-
if (isMaskAgnostic(VType))
196-
OS << ", ma";
197-
else
198-
OS << ", mu";
199-
}
200-
201-
unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
202-
unsigned LMul;
203-
bool Fractional;
204-
std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
205-
206-
// Convert LMul to a fixed point value with 3 fractional bits.
207-
LMul = Fractional ? (8 / LMul) : (LMul * 8);
208-
209-
assert(SEW >= 8 && "Unexpected SEW value");
210-
return (SEW * 8) / LMul;
211-
}
212-
213-
std::optional<RISCVII::VLMUL>
214-
RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) {
215-
unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
216-
unsigned EMULFixedPoint = (EEW * 8) / Ratio;
217-
bool Fractional = EMULFixedPoint < 8;
218-
unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
219-
if (!isValidLMUL(EMUL, Fractional))
220-
return std::nullopt;
221-
return RISCVVType::encodeLMUL(EMUL, Fractional);
222-
}
223-
224137
// Include the auto-generated portion of the compress emitter.
225138
#define GEN_UNCOMPRESS_INSTR
226139
#define GEN_COMPRESS_INSTR

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

Lines changed: 1 addition & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
#include "llvm/ADT/StringSwitch.h"
2121
#include "llvm/MC/MCInstrDesc.h"
2222
#include "llvm/Support/RISCVISAInfo.h"
23+
#include "llvm/TargetParser/RISCVTargetParser.h"
2324
#include "llvm/TargetParser/SubtargetFeature.h"
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2526
namespace llvm {
@@ -124,23 +125,6 @@ enum {
124125
TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
125126
};
126127

127-
enum VLMUL : uint8_t {
128-
LMUL_1 = 0,
129-
LMUL_2,
130-
LMUL_4,
131-
LMUL_8,
132-
LMUL_RESERVED,
133-
LMUL_F8,
134-
LMUL_F4,
135-
LMUL_F2
136-
};
137-
138-
enum {
139-
TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
140-
TAIL_AGNOSTIC = 1,
141-
MASK_AGNOSTIC = 2,
142-
};
143-
144128
// Helper functions to read TSFlags.
145129
/// \returns the format of the instruction.
146130
static inline unsigned getFormat(uint64_t TSFlags) {
@@ -484,61 +468,6 @@ parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
484468

485469
} // namespace RISCVFeatures
486470

487-
namespace RISCVVType {
488-
// Is this a SEW value that can be encoded into the VTYPE format.
489-
inline static bool isValidSEW(unsigned SEW) {
490-
return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
491-
}
492-
493-
// Is this a LMUL value that can be encoded into the VTYPE format.
494-
inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
495-
return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
496-
}
497-
498-
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
499-
bool MaskAgnostic);
500-
501-
inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
502-
unsigned VLMUL = VType & 0x7;
503-
return static_cast<RISCVII::VLMUL>(VLMUL);
504-
}
505-
506-
// Decode VLMUL into 1,2,4,8 and fractional indicator.
507-
std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
508-
509-
inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
510-
assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
511-
unsigned LmulLog2 = Log2_32(LMUL);
512-
return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
513-
}
514-
515-
inline static unsigned decodeVSEW(unsigned VSEW) {
516-
assert(VSEW < 8 && "Unexpected VSEW value");
517-
return 1 << (VSEW + 3);
518-
}
519-
520-
inline static unsigned encodeSEW(unsigned SEW) {
521-
assert(isValidSEW(SEW) && "Unexpected SEW value");
522-
return Log2_32(SEW) - 3;
523-
}
524-
525-
inline static unsigned getSEW(unsigned VType) {
526-
unsigned VSEW = (VType >> 3) & 0x7;
527-
return decodeVSEW(VSEW);
528-
}
529-
530-
inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
531-
532-
inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
533-
534-
void printVType(unsigned VType, raw_ostream &OS);
535-
536-
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
537-
538-
std::optional<RISCVII::VLMUL>
539-
getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
540-
} // namespace RISCVVType
541-
542471
namespace RISCVRVC {
543472
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
544473
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);

‎llvm/lib/Target/RISCV/RISCVISelLowering.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,6 @@
1818
#include "llvm/CodeGen/CallingConvLower.h"
1919
#include "llvm/CodeGen/SelectionDAG.h"
2020
#include "llvm/CodeGen/TargetLowering.h"
21-
#include "llvm/TargetParser/RISCVTargetParser.h"
2221
#include <optional>
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2423
namespace llvm {

‎llvm/lib/TargetParser/RISCVTargetParser.cpp‎

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -120,4 +120,95 @@ void getFeaturesForCPU(StringRef CPU,
120120
EnabledFeatures.push_back(F.substr(1));
121121
}
122122
} // namespace RISCV
123+
124+
namespace RISCVVType {
125+
// Encode VTYPE into the binary format used by the the VSETVLI instruction which
126+
// is used by our MC layer representation.
127+
//
128+
// Bits | Name | Description
129+
// -----+------------+------------------------------------------------
130+
// 7 | vma | Vector mask agnostic
131+
// 6 | vta | Vector tail agnostic
132+
// 5:3 | vsew[2:0] | Standard element width (SEW) setting
133+
// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
134+
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
135+
bool MaskAgnostic) {
136+
assert(isValidSEW(SEW) && "Invalid SEW");
137+
unsigned VLMULBits = static_cast<unsigned>(VLMUL);
138+
unsigned VSEWBits = encodeSEW(SEW);
139+
unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
140+
if (TailAgnostic)
141+
VTypeI |= 0x40;
142+
if (MaskAgnostic)
143+
VTypeI |= 0x80;
144+
145+
return VTypeI;
146+
}
147+
148+
std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL) {
149+
switch (VLMUL) {
150+
default:
151+
llvm_unreachable("Unexpected LMUL value!");
152+
case RISCVII::VLMUL::LMUL_1:
153+
case RISCVII::VLMUL::LMUL_2:
154+
case RISCVII::VLMUL::LMUL_4:
155+
case RISCVII::VLMUL::LMUL_8:
156+
return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
157+
case RISCVII::VLMUL::LMUL_F2:
158+
case RISCVII::VLMUL::LMUL_F4:
159+
case RISCVII::VLMUL::LMUL_F8:
160+
return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
161+
}
162+
}
163+
164+
void printVType(unsigned VType, raw_ostream &OS) {
165+
unsigned Sew = getSEW(VType);
166+
OS << "e" << Sew;
167+
168+
unsigned LMul;
169+
bool Fractional;
170+
std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
171+
172+
if (Fractional)
173+
OS << ", mf";
174+
else
175+
OS << ", m";
176+
OS << LMul;
177+
178+
if (isTailAgnostic(VType))
179+
OS << ", ta";
180+
else
181+
OS << ", tu";
182+
183+
if (isMaskAgnostic(VType))
184+
OS << ", ma";
185+
else
186+
OS << ", mu";
187+
}
188+
189+
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
190+
unsigned LMul;
191+
bool Fractional;
192+
std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
193+
194+
// Convert LMul to a fixed point value with 3 fractional bits.
195+
LMul = Fractional ? (8 / LMul) : (LMul * 8);
196+
197+
assert(SEW >= 8 && "Unexpected SEW value");
198+
return (SEW * 8) / LMul;
199+
}
200+
201+
std::optional<RISCVII::VLMUL>
202+
getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) {
203+
unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
204+
unsigned EMULFixedPoint = (EEW * 8) / Ratio;
205+
bool Fractional = EMULFixedPoint < 8;
206+
unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
207+
if (!isValidLMUL(EMUL, Fractional))
208+
return std::nullopt;
209+
return RISCVVType::encodeLMUL(EMUL, Fractional);
210+
}
211+
212+
} // namespace RISCVVType
213+
123214
} // namespace llvm

‎llvm/unittests/Target/RISCV/CMakeLists.txt‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,6 @@ set(LLVM_LINK_COMPONENTS
1616

1717
add_llvm_target_unittest(RISCVTests
1818
MCInstrAnalysisTest.cpp
19-
RISCVBaseInfoTest.cpp
2019
RISCVInstrInfoTest.cpp
2120
)
2221

‎llvm/unittests/TargetParser/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@ set(LLVM_LINK_COMPONENTS
66
add_llvm_unittest(TargetParserTests
77
CSKYTargetParserTest.cpp
88
Host.cpp
9+
RISCVTargetParserTest.cpp
910
TargetParserTest.cpp
1011
TripleTest.cpp
1112
)

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