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[SelectionDAG] Remove LegalTypes argument from getShiftAmountConstant. (#97653)
#97645 proposed to remove LegalTypes from getShiftAmountTy. This patches removes it from getShiftAmountConstant which is one of the callers of getShiftAmountTy.
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4 files changed

+20
-30
lines changed

4 files changed

+20
-30
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAG.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -680,10 +680,8 @@ class SelectionDAG {
680680
bool isTarget = false, bool isOpaque = false);
681681
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL,
682682
bool isTarget = false);
683-
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL,
684-
bool LegalTypes = true);
685-
SDValue getShiftAmountConstant(const APInt &Val, EVT VT, const SDLoc &DL,
686-
bool LegalTypes = true);
683+
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL);
684+
SDValue getShiftAmountConstant(const APInt &Val, EVT VT, const SDLoc &DL);
687685
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL,
688686
bool isTarget = false);
689687

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9293,11 +9293,10 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
92939293
return NewLoad;
92949294

92959295
SDValue ShiftedLoad =
9296-
NeedsZext
9297-
? DAG.getNode(ISD::SHL, SDLoc(N), VT, NewLoad,
9298-
DAG.getShiftAmountConstant(ZeroExtendedBytes * 8, VT,
9299-
SDLoc(N), LegalOperations))
9300-
: NewLoad;
9296+
NeedsZext ? DAG.getNode(ISD::SHL, SDLoc(N), VT, NewLoad,
9297+
DAG.getShiftAmountConstant(ZeroExtendedBytes * 8,
9298+
VT, SDLoc(N)))
9299+
: NewLoad;
93019300
return DAG.getNode(ISD::BSWAP, SDLoc(N), VT, ShiftedLoad);
93029301
}
93039302

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1752,14 +1752,14 @@ SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, const SDLoc &DL,
17521752
}
17531753

17541754
SDValue SelectionDAG::getShiftAmountConstant(uint64_t Val, EVT VT,
1755-
const SDLoc &DL, bool LegalTypes) {
1755+
const SDLoc &DL) {
17561756
assert(VT.isInteger() && "Shift amount is not an integer type!");
17571757
EVT ShiftVT = TLI->getShiftAmountTy(VT, getDataLayout());
17581758
return getConstant(Val, DL, ShiftVT);
17591759
}
17601760

17611761
SDValue SelectionDAG::getShiftAmountConstant(const APInt &Val, EVT VT,
1762-
const SDLoc &DL, bool LegalTypes) {
1762+
const SDLoc &DL) {
17631763
assert(Val.ult(VT.getScalarSizeInBits()) && "Out of range shift");
17641764
return getShiftAmountConstant(Val.getZExtValue(), VT, DL);
17651765
}

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 12 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1880,8 +1880,8 @@ bool TargetLowering::SimplifyDemandedBits(
18801880
Flags.setNoSignedWrap(IsNSW);
18811881
Flags.setNoUnsignedWrap(IsNUW);
18821882
SDValue NewOp = TLO.DAG.getNode(ISD::TRUNCATE, dl, HalfVT, Op0);
1883-
SDValue NewShiftAmt = TLO.DAG.getShiftAmountConstant(
1884-
ShAmt, HalfVT, dl, TLO.LegalTypes());
1883+
SDValue NewShiftAmt =
1884+
TLO.DAG.getShiftAmountConstant(ShAmt, HalfVT, dl);
18851885
SDValue NewShift = TLO.DAG.getNode(ISD::SHL, dl, HalfVT, NewOp,
18861886
NewShiftAmt, Flags);
18871887
SDValue NewExt =
@@ -1977,8 +1977,8 @@ bool TargetLowering::SimplifyDemandedBits(
19771977
((InDemandedMask.countLeadingZeros() >= (BitWidth / 2)) ||
19781978
TLO.DAG.MaskedValueIsZero(Op0, HiBits))) {
19791979
SDValue NewOp = TLO.DAG.getNode(ISD::TRUNCATE, dl, HalfVT, Op0);
1980-
SDValue NewShiftAmt = TLO.DAG.getShiftAmountConstant(
1981-
ShAmt, HalfVT, dl, TLO.LegalTypes());
1980+
SDValue NewShiftAmt =
1981+
TLO.DAG.getShiftAmountConstant(ShAmt, HalfVT, dl);
19821982
SDValue NewShift =
19831983
TLO.DAG.getNode(ISD::SRL, dl, HalfVT, NewOp, NewShiftAmt);
19841984
return TLO.CombineTo(
@@ -2600,8 +2600,7 @@ bool TargetLowering::SimplifyDemandedBits(
26002600
if (!(HighBits & DemandedBits)) {
26012601
// None of the shifted in bits are needed. Add a truncate of the
26022602
// shift input, then shift it.
2603-
SDValue NewShAmt =
2604-
TLO.DAG.getShiftAmountConstant(ShVal, VT, dl, TLO.LegalTypes());
2603+
SDValue NewShAmt = TLO.DAG.getShiftAmountConstant(ShVal, VT, dl);
26052604
SDValue NewTrunc =
26062605
TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, Src.getOperand(0));
26072606
return TLO.CombineTo(
@@ -4254,8 +4253,7 @@ SDValue TargetLowering::foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1,
42544253
return SDValue();
42554254

42564255
// (X - Y) == Y --> X == Y << 1
4257-
SDValue One =
4258-
DAG.getShiftAmountConstant(1, OpVT, DL, !DCI.isBeforeLegalize());
4256+
SDValue One = DAG.getShiftAmountConstant(1, OpVT, DL);
42594257
SDValue YShl1 = DAG.getNode(ISD::SHL, DL, N1.getValueType(), Y, One);
42604258
if (!DCI.isCalledByLegalizer())
42614259
DCI.AddToWorklist(YShl1.getNode());
@@ -5113,8 +5111,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
51135111
return DAG.getNode(
51145112
ISD::TRUNCATE, dl, VT,
51155113
DAG.getNode(ISD::SRL, dl, ShValTy, N0,
5116-
DAG.getShiftAmountConstant(
5117-
ShCt, ShValTy, dl, !DCI.isBeforeLegalize())));
5114+
DAG.getShiftAmountConstant(ShCt, ShValTy, dl)));
51185115
}
51195116
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
51205117
// (X & 8) == 8 --> (X & 8) >> 3
@@ -5125,8 +5122,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
51255122
return DAG.getNode(
51265123
ISD::TRUNCATE, dl, VT,
51275124
DAG.getNode(ISD::SRL, dl, ShValTy, N0,
5128-
DAG.getShiftAmountConstant(
5129-
ShCt, ShValTy, dl, !DCI.isBeforeLegalize())));
5125+
DAG.getShiftAmountConstant(ShCt, ShValTy, dl)));
51305126
}
51315127
}
51325128
}
@@ -5144,8 +5140,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
51445140
if (!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) {
51455141
SDValue Shift = DAG.getNode(
51465142
ISD::SRL, dl, ShValTy, N0.getOperand(0),
5147-
DAG.getShiftAmountConstant(ShiftBits, ShValTy, dl,
5148-
!DCI.isBeforeLegalize()));
5143+
DAG.getShiftAmountConstant(ShiftBits, ShValTy, dl));
51495144
SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy);
51505145
return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
51515146
}
@@ -5174,8 +5169,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
51745169
!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) {
51755170
SDValue Shift =
51765171
DAG.getNode(ISD::SRL, dl, ShValTy, N0,
5177-
DAG.getShiftAmountConstant(ShiftBits, ShValTy, dl,
5178-
!DCI.isBeforeLegalize()));
5172+
DAG.getShiftAmountConstant(ShiftBits, ShValTy, dl));
51795173
SDValue CmpRHS = DAG.getConstant(NewC, dl, ShValTy);
51805174
return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
51815175
}
@@ -9599,9 +9593,8 @@ TargetLowering::scalarizeVectorLoad(LoadSDNode *LD,
95999593
for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
96009594
unsigned ShiftIntoIdx =
96019595
(DAG.getDataLayout().isBigEndian() ? (NumElem - 1) - Idx : Idx);
9602-
SDValue ShiftAmount =
9603-
DAG.getShiftAmountConstant(ShiftIntoIdx * SrcEltVT.getSizeInBits(),
9604-
LoadVT, SL, /*LegalTypes=*/false);
9596+
SDValue ShiftAmount = DAG.getShiftAmountConstant(
9597+
ShiftIntoIdx * SrcEltVT.getSizeInBits(), LoadVT, SL);
96059598
SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount);
96069599
SDValue Elt =
96079600
DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask);

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