Skip to content

Commit 839a8fe

Browse files
authored
AMDGPU: Copy SubtargetPredicate from pseudo to real for dpp16 and dpp8 (#84517)
We usually expect to copy SubtargetPredicate (and OtherPredicates) from pseudo to real. However, in dpp16 and dpp8, there are assignments like SubtargetPredicate = HasDPP/HasDPP16/HasDpp8. These assignments override predicates copied from pseudo, and thus the predicates used to define pseudo get lost. Losing predicates is a subtle issue usually not easy to be found. It may result in instructions being generated on GPUs that do not support the features to generate them. #84354 addressed one of such issues, and inspired this work. Fortunately, we found that the assignment of SubtargetPredicate usually comes together with assignment of AssemblerPredicate, and with the same value. For example: let AssemblerPredicate = HasDPP16; let SubtargetPredicate = HasDPP16; One of them is redundant and can be removed. In this work, we remove the redundant assignment of SubtargetPredicate, and then copy it from pseudo for VOP*_DPP and VOP*_DPP8. With this change, we can safely use SubtargetPredicate to define pseudo instructions.
1 parent a456885 commit 839a8fe

File tree

4 files changed

+8
-7
lines changed

4 files changed

+8
-7
lines changed

llvm/lib/Target/AMDGPU/VOP1Instructions.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -730,6 +730,7 @@ class VOP1_DPP<bits<8> op, VOP1_DPP_Pseudo ps, VOPProfile p = ps.Pfl, bit isDPP1
730730
let SchedRW = ps.SchedRW;
731731
let Uses = ps.Uses;
732732
let TRANS = ps.TRANS;
733+
let SubtargetPredicate = ps.SubtargetPredicate;
733734
let OtherPredicates = ps.OtherPredicates;
734735

735736
bits<8> vdst;
@@ -743,7 +744,6 @@ class VOP1_DPP16<bits<8> op, VOP1_DPP_Pseudo ps, int subtarget, VOPProfile p = p
743744
VOP1_DPP<op, ps, p, 1>,
744745
SIMCInstr <ps.PseudoInstr, subtarget> {
745746
let AssemblerPredicate = HasDPP16;
746-
let SubtargetPredicate = HasDPP16;
747747
}
748748

749749
class VOP1_DPP16_Gen<bits<8> op, VOP1_DPP_Pseudo ps, GFXGen Gen, VOPProfile p = ps.Pfl> :
@@ -758,6 +758,7 @@ class VOP1_DPP8<bits<8> op, VOP1_Pseudo ps, VOPProfile p = ps.Pfl> :
758758
let Defs = ps.Defs;
759759
let SchedRW = ps.SchedRW;
760760
let Uses = ps.Uses;
761+
let SubtargetPredicate = ps.SubtargetPredicate;
761762
let OtherPredicates = ps.OtherPredicates;
762763

763764
bits<8> vdst;

llvm/lib/Target/AMDGPU/VOP2Instructions.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1259,7 +1259,7 @@ class Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
12591259
string opName = ps.OpName, VOPProfile p = ps.Pfl> :
12601260
VOP2_DPP<op, ps, opName, p, 1> {
12611261
let AssemblerPredicate = HasDPP16;
1262-
let SubtargetPredicate = HasDPP16;
1262+
let SubtargetPredicate = ps.SubtargetPredicate;
12631263
let OtherPredicates = ps.OtherPredicates;
12641264
}
12651265

@@ -1294,6 +1294,7 @@ class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps,
12941294
let Inst{30-25} = op;
12951295
let Inst{31} = 0x0;
12961296

1297+
let SubtargetPredicate = ps.SubtargetPredicate;
12971298
let OtherPredicates = ps.OtherPredicates;
12981299
}
12991300

llvm/lib/Target/AMDGPU/VOP3PInstructions.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1353,7 +1353,7 @@ class VOP3P_DPP16<bits<7> op, VOP_DPP_Pseudo ps, int subtarget,
13531353
let SchedRW = ps.SchedRW;
13541354
let Uses = ps.Uses;
13551355
let AssemblerPredicate = HasDPP16;
1356-
let SubtargetPredicate = HasDPP16;
1356+
let SubtargetPredicate = ps.SubtargetPredicate;
13571357
let OtherPredicates = ps.OtherPredicates;
13581358
let IsPacked = ps.IsPacked;
13591359
}
@@ -1364,6 +1364,7 @@ class VOP3P_DPP8_Base<bits<7> op, VOP_Pseudo ps, string opName = ps.OpName>
13641364
let Defs = ps.Defs;
13651365
let SchedRW = ps.SchedRW;
13661366
let Uses = ps.Uses;
1367+
let SubtargetPredicate = ps.SubtargetPredicate;
13671368
let OtherPredicates = ps.OtherPredicates;
13681369
let IsPacked = ps.IsPacked;
13691370
}

llvm/lib/Target/AMDGPU/VOPInstructions.td

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -832,7 +832,6 @@ class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[],
832832
string AsmOperands = asmOps;
833833

834834
let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", "");
835-
let SubtargetPredicate = !if(P.HasExt64BitDPP, HasDPALU_DPP, HasDPP);
836835
let AssemblerPredicate = !if(P.HasExt64BitDPP, HasDPALU_DPP, HasDPP);
837836
let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
838837
AMDGPUAsmVariants.Disable);
@@ -903,7 +902,6 @@ class VOP_DPP_Base <string OpName, VOPProfile P,
903902
let Size = 8;
904903

905904
let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", "");
906-
let SubtargetPredicate = !if(P.HasExt64BitDPP, HasDPALU_DPP, HasDPP);
907905
let AssemblerPredicate = !if(P.HasExt64BitDPP, HasDPALU_DPP, HasDPP);
908906
let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
909907
AMDGPUAsmVariants.Disable);
@@ -993,7 +991,6 @@ class VOP_DPP8_Base<string OpName, VOPProfile P, dag InsDPP8 = P.InsDPP8, string
993991
let Size = 8;
994992

995993
let AsmMatchConverter = "cvtDPP8";
996-
let SubtargetPredicate = HasDPP8;
997994
let AssemblerPredicate = HasDPP8;
998995
let AsmVariantName = AMDGPUAsmVariants.DPP;
999996
let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", "");
@@ -1340,7 +1337,7 @@ class Base_VOP3_DPP16<bits<10> op, VOP_DPP_Pseudo ps, string opName = ps.OpName>
13401337
let SchedRW = ps.SchedRW;
13411338
let Uses = ps.Uses;
13421339
let AssemblerPredicate = HasDPP16;
1343-
let SubtargetPredicate = HasDPP16;
1340+
let SubtargetPredicate = ps.SubtargetPredicate;
13441341
let OtherPredicates = ps.OtherPredicates;
13451342
}
13461343

@@ -1366,6 +1363,7 @@ class Base_VOP3_DPP8<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
13661363
let SchedRW = ps.SchedRW;
13671364
let Uses = ps.Uses;
13681365

1366+
let SubtargetPredicate = ps.SubtargetPredicate;
13691367
let OtherPredicates = ps.OtherPredicates;
13701368
}
13711369

0 commit comments

Comments
 (0)