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[X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to
avoid static check fail RegClassOrBank is an object of RegClassOrRegBank, which is defined as using llvm::RegClassOrRegBank = typedef PointerUnion<const TargetRegisterClass *, const RegisterBank *> so control flow can not get here. Use ""llvm_unreachable" here to avoid "null pointer" confusion. Patch by Shengchen Kan (skan) Differential Revision: https://reviews.llvm.org/D62006 Signed-off-by: pengfei <[email protected]> llvm-svn: 361912
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-4
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2 files changed

+6
-4
lines changed

llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,9 @@ RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
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return RB;
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if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
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return &getRegBankFromRegClass(*RC);
94-
return nullptr;
94+
95+
llvm_unreachable("RegClassOrBank is either a const RegisterBank* or "
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"a const TargetRegisterClass*");
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}
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9799
const TargetRegisterClass &

llvm/lib/Target/X86/X86InstructionSelector.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1610,8 +1610,8 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I,
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assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&
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"Arguments and return value types must match");
16121612

1613-
const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);
1614-
if (!RegRB || RegRB->getID() != X86::GPRRegBankID)
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const RegisterBank &RegRB = *RBI.getRegBank(DstReg, MRI, TRI);
1614+
if (RegRB.getID() != X86::GPRRegBankID)
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return false;
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16171617
const static unsigned NumTypes = 4; // i8, i16, i32, i64
@@ -1709,7 +1709,7 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I,
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const DivRemEntry &TypeEntry = *OpEntryIt;
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const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];
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1712-
const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB);
1712+
const TargetRegisterClass *RegRC = getRegClass(RegTy, RegRB);
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if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) ||
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!RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) ||
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!RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {

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