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LU-JOHNLU-JOHN
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[AMDGPU] Generate s_absdiff_i32 (#164835)
Generate s_absdiff_i32. Tested in absdiff.ll. Also update s_cmp_0.ll to test that s_absdiff_i32 is foldable with a s_cmp_lg_u32 sX, 0. --------- Signed-off-by: John Lu <[email protected]>
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‎llvm/lib/Target/AMDGPU/SOPInstructions.td‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -838,9 +838,10 @@ def S_CBRANCH_G_FORK : SOP2_Pseudo <
838838
let SubtargetPredicate = isGFX6GFX7GFX8GFX9;
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}
840840

841-
let Defs = [SCC] in {
842-
def S_ABSDIFF_I32 : SOP2_32 <"s_absdiff_i32">;
843-
} // End Defs = [SCC]
841+
let isCommutable = 1, Defs = [SCC] in
842+
def S_ABSDIFF_I32 : SOP2_32 <"s_absdiff_i32",
843+
[(set i32:$sdst, (UniformUnaryFrag<abs> (sub_oneuse i32:$src0, i32:$src1)))]
844+
>;
844845

845846
let SubtargetPredicate = isGFX8GFX9 in {
846847
def S_RFE_RESTORE_B64 : SOP2_Pseudo <

‎llvm/test/CodeGen/AMDGPU/absdiff.ll‎

Lines changed: 104 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,104 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s
3+
4+
define amdgpu_ps i16 @absdiff_i16_false(i16 inreg %arg0, i16 inreg %arg1) {
5+
; CHECK-LABEL: absdiff_i16_false:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_sub_i32 s0, s0, s1
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; CHECK-NEXT: s_sext_i32_i16 s1, s0
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; CHECK-NEXT: s_sub_i32 s0, 0, s0
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; CHECK-NEXT: s_sext_i32_i16 s0, s0
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; CHECK-NEXT: s_max_i32 s0, s1, s0
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; CHECK-NEXT: ; return to shader part epilog
13+
%diff = sub i16 %arg0, %arg1
14+
%res = call i16 @llvm.abs.i16(i16 %diff, i1 false) ; INT_MIN input returns INT_MIN
15+
ret i16 %res
16+
}
17+
18+
define amdgpu_ps i16 @absdiff_i16_true(i16 inreg %arg0, i16 inreg %arg1) {
19+
; CHECK-LABEL: absdiff_i16_true:
20+
; CHECK: ; %bb.0:
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; CHECK-NEXT: s_sub_i32 s0, s0, s1
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; CHECK-NEXT: s_sext_i32_i16 s1, s0
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; CHECK-NEXT: s_sub_i32 s0, 0, s0
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; CHECK-NEXT: s_sext_i32_i16 s0, s0
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; CHECK-NEXT: s_max_i32 s0, s1, s0
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; CHECK-NEXT: ; return to shader part epilog
27+
%diff = sub i16 %arg0, %arg1
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%res = call i16 @llvm.abs.i16(i16 %diff, i1 true) ; INT_MIN input returns poison
29+
ret i16 %res
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}
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32+
define amdgpu_ps i32 @absdiff_i32_false(i32 inreg %arg0, i32 inreg %arg1) {
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; CHECK-LABEL: absdiff_i32_false:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_absdiff_i32 s0, s0, s1
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; CHECK-NEXT: ; return to shader part epilog
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%diff = sub i32 %arg0, %arg1
38+
%res = call i32 @llvm.abs.i32(i32 %diff, i1 false) ; INT_MIN input returns INT_MIN
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ret i32 %res
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}
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define amdgpu_ps i32 @absdiff_i32_true(i32 inreg %arg0, i32 inreg %arg1) {
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; CHECK-LABEL: absdiff_i32_true:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_absdiff_i32 s0, s0, s1
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; CHECK-NEXT: ; return to shader part epilog
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%diff = sub i32 %arg0, %arg1
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%res = call i32 @llvm.abs.i32(i32 %diff, i1 true) ; INT_MIN input returns poison
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ret i32 %res
50+
}
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; Multiple uses of %diff. No benefit for using s_absdiff_i32.
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define amdgpu_ps i32 @absdiff_i32_false_multi_use(i32 inreg %arg0, i32 inreg %arg1) {
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; CHECK-LABEL: absdiff_i32_false_multi_use:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_sub_i32 s1, s0, s1
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; CHECK-NEXT: s_abs_i32 s0, s1
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s1
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ; return to shader part epilog
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%diff = sub i32 %arg0, %arg1
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%res = call i32 @llvm.abs.i32(i32 %diff, i1 false) ; INT_MIN input returns INT_MIN
64+
call void asm "; use $0", "s"(i32 %diff)
65+
ret i32 %res
66+
}
67+
68+
define <2 x i32> @absdiff_2xi32_false(<2 x i32> %arg0, <2 x i32> %arg1) {
69+
; CHECK-LABEL: absdiff_2xi32_false:
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; CHECK: ; %bb.0:
71+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
72+
; CHECK-NEXT: v_sub_u32_e32 v0, v0, v2
73+
; CHECK-NEXT: v_sub_u32_e32 v1, v1, v3
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; CHECK-NEXT: v_sub_u32_e32 v2, 0, v0
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; CHECK-NEXT: v_max_i32_e32 v0, v2, v0
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; CHECK-NEXT: v_sub_u32_e32 v2, 0, v1
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; CHECK-NEXT: v_max_i32_e32 v1, v2, v1
78+
; CHECK-NEXT: s_setpc_b64 s[30:31]
79+
%diff = sub <2 x i32> %arg0, %arg1
80+
%res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %diff, i1 false) ; INT_MIN input returns INT_MIN
81+
ret <2 x i32> %res
82+
}
83+
84+
define <4 x i32> @absdiff_4xi32_false(<4 x i32> %arg0, <4 x i32> %arg1) {
85+
; CHECK-LABEL: absdiff_4xi32_false:
86+
; CHECK: ; %bb.0:
87+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
88+
; CHECK-NEXT: v_sub_u32_e32 v0, v0, v4
89+
; CHECK-NEXT: v_sub_u32_e32 v1, v1, v5
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; CHECK-NEXT: v_sub_u32_e32 v4, 0, v0
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; CHECK-NEXT: v_sub_u32_e32 v2, v2, v6
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; CHECK-NEXT: v_max_i32_e32 v0, v4, v0
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; CHECK-NEXT: v_sub_u32_e32 v4, 0, v1
94+
; CHECK-NEXT: v_sub_u32_e32 v3, v3, v7
95+
; CHECK-NEXT: v_max_i32_e32 v1, v4, v1
96+
; CHECK-NEXT: v_sub_u32_e32 v4, 0, v2
97+
; CHECK-NEXT: v_max_i32_e32 v2, v4, v2
98+
; CHECK-NEXT: v_sub_u32_e32 v4, 0, v3
99+
; CHECK-NEXT: v_max_i32_e32 v3, v4, v3
100+
; CHECK-NEXT: s_setpc_b64 s[30:31]
101+
%diff = sub <4 x i32> %arg0, %arg1
102+
%res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %diff, i1 false) ; INT_MIN input returns INT_MIN
103+
ret <4 x i32> %res
104+
}

‎llvm/test/CodeGen/AMDGPU/s_cmp_0.ll‎

Lines changed: 20 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,21 @@ define amdgpu_ps i32 @abs32(i32 inreg %val0) {
110110
ret i32 %zext
111111
}
112112

113+
define amdgpu_ps i32 @absdiff32(i32 inreg %val0, i32 inreg %val1) {
114+
; CHECK-LABEL: absdiff32:
115+
; CHECK: ; %bb.0:
116+
; CHECK-NEXT: s_absdiff_i32 s0, s0, s1
117+
; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
118+
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
119+
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
120+
; CHECK-NEXT: ; return to shader part epilog
121+
%diff = sub i32 %val0, %val1
122+
%result = call i32 @llvm.abs.i32(i32 %diff, i1 false)
123+
%cmp = icmp ne i32 %result, 0
124+
%zext = zext i1 %cmp to i32
125+
ret i32 %zext
126+
}
127+
113128
define amdgpu_ps i32 @and32(i32 inreg %val0, i32 inreg %val1) {
114129
; CHECK-LABEL: and32:
115130
; CHECK: ; %bb.0:
@@ -608,14 +623,14 @@ define amdgpu_ps i32 @si_pc_add_rel_offset_must_not_optimize() {
608623
; CHECK-NEXT: s_add_u32 s0, s0, __unnamed_1@rel32@lo+4
609624
; CHECK-NEXT: s_addc_u32 s1, s1, __unnamed_1@rel32@hi+12
610625
; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0
611-
; CHECK-NEXT: s_cbranch_scc0 .LBB35_2
626+
; CHECK-NEXT: s_cbranch_scc0 .LBB36_2
612627
; CHECK-NEXT: ; %bb.1: ; %endif
613628
; CHECK-NEXT: s_mov_b32 s0, 1
614-
; CHECK-NEXT: s_branch .LBB35_3
615-
; CHECK-NEXT: .LBB35_2: ; %if
629+
; CHECK-NEXT: s_branch .LBB36_3
630+
; CHECK-NEXT: .LBB36_2: ; %if
616631
; CHECK-NEXT: s_mov_b32 s0, 0
617-
; CHECK-NEXT: s_branch .LBB35_3
618-
; CHECK-NEXT: .LBB35_3:
632+
; CHECK-NEXT: s_branch .LBB36_3
633+
; CHECK-NEXT: .LBB36_3:
619634
%cmp = icmp ne ptr addrspace(4) @1, null
620635
br i1 %cmp, label %endif, label %if
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