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[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
This patch supports FP_TO_SINT, FP_TO_UINT, VP_FP_TO_SINT and VP_FP_TO_UINT for fp16 vectors input when we only have Zvfhmin but no Zvfh.
1 parent 701d804 commit 76fc871

11 files changed

+1579
-589
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5751,6 +5751,22 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
57515751
[[fallthrough]];
57525752
case ISD::FP_TO_SINT:
57535753
case ISD::FP_TO_UINT:
5754+
if (SDValue Op1 = Op.getOperand(0);
5755+
Op1.getValueType().isVector() &&
5756+
Op1.getValueType().getScalarType() == MVT::f16 &&
5757+
(Subtarget.hasVInstructionsF16Minimal() &&
5758+
!Subtarget.hasVInstructionsF16())) {
5759+
if (Op1.getValueType() == MVT::nxv32f16)
5760+
return SplitVectorOp(Op, DAG);
5761+
// f16 -> f32
5762+
SDLoc DL(Op);
5763+
MVT NVT = MVT::getVectorVT(MVT::f32,
5764+
Op1.getValueType().getVectorElementCount());
5765+
SDValue WidenVec = DAG.getNode(ISD::FP_EXTEND, DL, NVT, Op1);
5766+
// f32 -> int
5767+
return DAG.getNode(Op.getOpcode(), DL, Op.getValueType(), WidenVec);
5768+
}
5769+
[[fallthrough]];
57545770
case ISD::STRICT_FP_TO_SINT:
57555771
case ISD::STRICT_FP_TO_UINT:
57565772
case ISD::STRICT_SINT_TO_FP:
@@ -6297,6 +6313,22 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
62976313
[[fallthrough]];
62986314
case ISD::VP_FP_TO_SINT:
62996315
case ISD::VP_FP_TO_UINT:
6316+
if (SDValue Op1 = Op.getOperand(0);
6317+
Op1.getValueType().isVector() &&
6318+
Op1.getValueType().getScalarType() == MVT::f16 &&
6319+
(Subtarget.hasVInstructionsF16Minimal() &&
6320+
!Subtarget.hasVInstructionsF16())) {
6321+
if (Op1.getValueType() == MVT::nxv32f16)
6322+
return SplitVPOp(Op, DAG);
6323+
// f16 -> f32
6324+
SDLoc DL(Op);
6325+
MVT NVT = MVT::getVectorVT(MVT::f32,
6326+
Op1.getValueType().getVectorElementCount());
6327+
SDValue WidenVec = DAG.getNode(ISD::FP_EXTEND, DL, NVT, Op1);
6328+
// f32 -> int
6329+
return DAG.getNode(Op.getOpcode(), DL, Op.getValueType(),
6330+
{WidenVec, Op.getOperand(1), Op.getOperand(2)});
6331+
}
63006332
return lowerVPFPIntConvOp(Op, DAG);
63016333
case ISD::VP_SETCC:
63026334
if (Op.getOperand(0).getSimpleValueType() == MVT::nxv32f16 &&

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

Lines changed: 142 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,12 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8RV32
3-
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8RV64
4-
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1RV32
5-
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1RV64
2+
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8RV32,LMULMAX8RV32ZVFH
3+
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8RV64,LMULMAX8RV64ZVFH
4+
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1RV32,LMULMAX1RV32ZVFH
5+
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1RV64,LMULMAX1RV64ZVFH
6+
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+f,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8RV32,LMULMAX8RV32ZVFHMIN
7+
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+f,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8RV64,LMULMAX8RV64ZVFHMIN
8+
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+f,+d -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1RV32,LMULMAX1RV32ZVFHMIN
9+
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+f,+d -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1RV64,LMULMAX1RV64ZVFHMIN
610

711
define void @fp2si_v2f32_v2i32(ptr %x, ptr %y) {
812
; CHECK-LABEL: fp2si_v2f32_v2i32:
@@ -589,25 +593,145 @@ define void @fp2ui_v2f16_v2i64(ptr %x, ptr %y) {
589593
}
590594

591595
define <2 x i1> @fp2si_v2f16_v2i1(<2 x half> %x) {
592-
; CHECK-LABEL: fp2si_v2f16_v2i1:
593-
; CHECK: # %bb.0:
594-
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
595-
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
596-
; CHECK-NEXT: vand.vi v8, v9, 1
597-
; CHECK-NEXT: vmsne.vi v0, v8, 0
598-
; CHECK-NEXT: ret
596+
; LMULMAX8RV32ZVFH-LABEL: fp2si_v2f16_v2i1:
597+
; LMULMAX8RV32ZVFH: # %bb.0:
598+
; LMULMAX8RV32ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
599+
; LMULMAX8RV32ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
600+
; LMULMAX8RV32ZVFH-NEXT: vand.vi v8, v9, 1
601+
; LMULMAX8RV32ZVFH-NEXT: vmsne.vi v0, v8, 0
602+
; LMULMAX8RV32ZVFH-NEXT: ret
603+
;
604+
; LMULMAX8RV64ZVFH-LABEL: fp2si_v2f16_v2i1:
605+
; LMULMAX8RV64ZVFH: # %bb.0:
606+
; LMULMAX8RV64ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
607+
; LMULMAX8RV64ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
608+
; LMULMAX8RV64ZVFH-NEXT: vand.vi v8, v9, 1
609+
; LMULMAX8RV64ZVFH-NEXT: vmsne.vi v0, v8, 0
610+
; LMULMAX8RV64ZVFH-NEXT: ret
611+
;
612+
; LMULMAX1RV32ZVFH-LABEL: fp2si_v2f16_v2i1:
613+
; LMULMAX1RV32ZVFH: # %bb.0:
614+
; LMULMAX1RV32ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
615+
; LMULMAX1RV32ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
616+
; LMULMAX1RV32ZVFH-NEXT: vand.vi v8, v9, 1
617+
; LMULMAX1RV32ZVFH-NEXT: vmsne.vi v0, v8, 0
618+
; LMULMAX1RV32ZVFH-NEXT: ret
619+
;
620+
; LMULMAX1RV64ZVFH-LABEL: fp2si_v2f16_v2i1:
621+
; LMULMAX1RV64ZVFH: # %bb.0:
622+
; LMULMAX1RV64ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
623+
; LMULMAX1RV64ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
624+
; LMULMAX1RV64ZVFH-NEXT: vand.vi v8, v9, 1
625+
; LMULMAX1RV64ZVFH-NEXT: vmsne.vi v0, v8, 0
626+
; LMULMAX1RV64ZVFH-NEXT: ret
627+
;
628+
; LMULMAX8RV32ZVFHMIN-LABEL: fp2si_v2f16_v2i1:
629+
; LMULMAX8RV32ZVFHMIN: # %bb.0:
630+
; LMULMAX8RV32ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
631+
; LMULMAX8RV32ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
632+
; LMULMAX8RV32ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
633+
; LMULMAX8RV32ZVFHMIN-NEXT: vand.vi v8, v8, 1
634+
; LMULMAX8RV32ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
635+
; LMULMAX8RV32ZVFHMIN-NEXT: ret
636+
;
637+
; LMULMAX8RV64ZVFHMIN-LABEL: fp2si_v2f16_v2i1:
638+
; LMULMAX8RV64ZVFHMIN: # %bb.0:
639+
; LMULMAX8RV64ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
640+
; LMULMAX8RV64ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
641+
; LMULMAX8RV64ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
642+
; LMULMAX8RV64ZVFHMIN-NEXT: vand.vi v8, v8, 1
643+
; LMULMAX8RV64ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
644+
; LMULMAX8RV64ZVFHMIN-NEXT: ret
645+
;
646+
; LMULMAX1RV32ZVFHMIN-LABEL: fp2si_v2f16_v2i1:
647+
; LMULMAX1RV32ZVFHMIN: # %bb.0:
648+
; LMULMAX1RV32ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
649+
; LMULMAX1RV32ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
650+
; LMULMAX1RV32ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
651+
; LMULMAX1RV32ZVFHMIN-NEXT: vand.vi v8, v8, 1
652+
; LMULMAX1RV32ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
653+
; LMULMAX1RV32ZVFHMIN-NEXT: ret
654+
;
655+
; LMULMAX1RV64ZVFHMIN-LABEL: fp2si_v2f16_v2i1:
656+
; LMULMAX1RV64ZVFHMIN: # %bb.0:
657+
; LMULMAX1RV64ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
658+
; LMULMAX1RV64ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
659+
; LMULMAX1RV64ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
660+
; LMULMAX1RV64ZVFHMIN-NEXT: vand.vi v8, v8, 1
661+
; LMULMAX1RV64ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
662+
; LMULMAX1RV64ZVFHMIN-NEXT: ret
599663
%z = fptosi <2 x half> %x to <2 x i1>
600664
ret <2 x i1> %z
601665
}
602666

603667
define <2 x i1> @fp2ui_v2f16_v2i1(<2 x half> %x) {
604-
; CHECK-LABEL: fp2ui_v2f16_v2i1:
605-
; CHECK: # %bb.0:
606-
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
607-
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
608-
; CHECK-NEXT: vand.vi v8, v9, 1
609-
; CHECK-NEXT: vmsne.vi v0, v8, 0
610-
; CHECK-NEXT: ret
668+
; LMULMAX8RV32ZVFH-LABEL: fp2ui_v2f16_v2i1:
669+
; LMULMAX8RV32ZVFH: # %bb.0:
670+
; LMULMAX8RV32ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
671+
; LMULMAX8RV32ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
672+
; LMULMAX8RV32ZVFH-NEXT: vand.vi v8, v9, 1
673+
; LMULMAX8RV32ZVFH-NEXT: vmsne.vi v0, v8, 0
674+
; LMULMAX8RV32ZVFH-NEXT: ret
675+
;
676+
; LMULMAX8RV64ZVFH-LABEL: fp2ui_v2f16_v2i1:
677+
; LMULMAX8RV64ZVFH: # %bb.0:
678+
; LMULMAX8RV64ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
679+
; LMULMAX8RV64ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
680+
; LMULMAX8RV64ZVFH-NEXT: vand.vi v8, v9, 1
681+
; LMULMAX8RV64ZVFH-NEXT: vmsne.vi v0, v8, 0
682+
; LMULMAX8RV64ZVFH-NEXT: ret
683+
;
684+
; LMULMAX1RV32ZVFH-LABEL: fp2ui_v2f16_v2i1:
685+
; LMULMAX1RV32ZVFH: # %bb.0:
686+
; LMULMAX1RV32ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
687+
; LMULMAX1RV32ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
688+
; LMULMAX1RV32ZVFH-NEXT: vand.vi v8, v9, 1
689+
; LMULMAX1RV32ZVFH-NEXT: vmsne.vi v0, v8, 0
690+
; LMULMAX1RV32ZVFH-NEXT: ret
691+
;
692+
; LMULMAX1RV64ZVFH-LABEL: fp2ui_v2f16_v2i1:
693+
; LMULMAX1RV64ZVFH: # %bb.0:
694+
; LMULMAX1RV64ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
695+
; LMULMAX1RV64ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
696+
; LMULMAX1RV64ZVFH-NEXT: vand.vi v8, v9, 1
697+
; LMULMAX1RV64ZVFH-NEXT: vmsne.vi v0, v8, 0
698+
; LMULMAX1RV64ZVFH-NEXT: ret
699+
;
700+
; LMULMAX8RV32ZVFHMIN-LABEL: fp2ui_v2f16_v2i1:
701+
; LMULMAX8RV32ZVFHMIN: # %bb.0:
702+
; LMULMAX8RV32ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
703+
; LMULMAX8RV32ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
704+
; LMULMAX8RV32ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
705+
; LMULMAX8RV32ZVFHMIN-NEXT: vand.vi v8, v8, 1
706+
; LMULMAX8RV32ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
707+
; LMULMAX8RV32ZVFHMIN-NEXT: ret
708+
;
709+
; LMULMAX8RV64ZVFHMIN-LABEL: fp2ui_v2f16_v2i1:
710+
; LMULMAX8RV64ZVFHMIN: # %bb.0:
711+
; LMULMAX8RV64ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
712+
; LMULMAX8RV64ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
713+
; LMULMAX8RV64ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
714+
; LMULMAX8RV64ZVFHMIN-NEXT: vand.vi v8, v8, 1
715+
; LMULMAX8RV64ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
716+
; LMULMAX8RV64ZVFHMIN-NEXT: ret
717+
;
718+
; LMULMAX1RV32ZVFHMIN-LABEL: fp2ui_v2f16_v2i1:
719+
; LMULMAX1RV32ZVFHMIN: # %bb.0:
720+
; LMULMAX1RV32ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
721+
; LMULMAX1RV32ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
722+
; LMULMAX1RV32ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
723+
; LMULMAX1RV32ZVFHMIN-NEXT: vand.vi v8, v8, 1
724+
; LMULMAX1RV32ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
725+
; LMULMAX1RV32ZVFHMIN-NEXT: ret
726+
;
727+
; LMULMAX1RV64ZVFHMIN-LABEL: fp2ui_v2f16_v2i1:
728+
; LMULMAX1RV64ZVFHMIN: # %bb.0:
729+
; LMULMAX1RV64ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
730+
; LMULMAX1RV64ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
731+
; LMULMAX1RV64ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
732+
; LMULMAX1RV64ZVFHMIN-NEXT: vand.vi v8, v8, 1
733+
; LMULMAX1RV64ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
734+
; LMULMAX1RV64ZVFHMIN-NEXT: ret
611735
%z = fptoui <2 x half> %x to <2 x i1>
612736
ret <2 x i1> %z
613737
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll

Lines changed: 34 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,27 +1,47 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s
3-
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s
2+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
3+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
4+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
5+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
46

57
declare <4 x i1> @llvm.vp.fptosi.v4i1.v4f16(<4 x half>, <4 x i1>, i32)
68

79
define <4 x i1> @vfptosi_v4i1_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {
8-
; CHECK-LABEL: vfptosi_v4i1_v4f16:
9-
; CHECK: # %bb.0:
10-
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
11-
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t
12-
; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
13-
; CHECK-NEXT: ret
10+
; ZVFH-LABEL: vfptosi_v4i1_v4f16:
11+
; ZVFH: # %bb.0:
12+
; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
13+
; ZVFH-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t
14+
; ZVFH-NEXT: vmsne.vi v0, v8, 0, v0.t
15+
; ZVFH-NEXT: ret
16+
;
17+
; ZVFHMIN-LABEL: vfptosi_v4i1_v4f16:
18+
; ZVFHMIN: # %bb.0:
19+
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
20+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
21+
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma
22+
; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t
23+
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0, v0.t
24+
; ZVFHMIN-NEXT: ret
1425
%v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
1526
ret <4 x i1> %v
1627
}
1728

1829
define <4 x i1> @vfptosi_v4i1_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
19-
; CHECK-LABEL: vfptosi_v4i1_v4f16_unmasked:
20-
; CHECK: # %bb.0:
21-
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
22-
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
23-
; CHECK-NEXT: vmsne.vi v0, v8, 0
24-
; CHECK-NEXT: ret
30+
; ZVFH-LABEL: vfptosi_v4i1_v4f16_unmasked:
31+
; ZVFH: # %bb.0:
32+
; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
33+
; ZVFH-NEXT: vfcvt.rtz.x.f.v v8, v8
34+
; ZVFH-NEXT: vmsne.vi v0, v8, 0
35+
; ZVFH-NEXT: ret
36+
;
37+
; ZVFHMIN-LABEL: vfptosi_v4i1_v4f16_unmasked:
38+
; ZVFHMIN: # %bb.0:
39+
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
40+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
41+
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma
42+
; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9
43+
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
44+
; ZVFHMIN-NEXT: ret
2545
%v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl)
2646
ret <4 x i1> %v
2747
}

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