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[AMDGPU] Use a generic printer for NamedIntOperands.
1 parent 9f08ae8 commit 768af48

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4 files changed

+40
-140
lines changed

4 files changed

+40
-140
lines changed

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 12 additions & 109 deletions
Original file line numberDiff line numberDiff line change
@@ -76,11 +76,6 @@ void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
7676
O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
7777
}
7878

79-
void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
80-
raw_ostream &O) {
81-
O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
82-
}
83-
8479
void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
8580
raw_ostream &O) {
8681
O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
@@ -135,24 +130,6 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
135130
}
136131
}
137132

138-
void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
139-
const MCSubtargetInfo &STI,
140-
raw_ostream &O) {
141-
if (MI->getOperand(OpNo).getImm()) {
142-
O << " offset0:";
143-
printU8ImmDecOperand(MI, OpNo, O);
144-
}
145-
}
146-
147-
void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
148-
const MCSubtargetInfo &STI,
149-
raw_ostream &O) {
150-
if (MI->getOperand(OpNo).getImm()) {
151-
O << " offset1:";
152-
printU8ImmDecOperand(MI, OpNo, O);
153-
}
154-
}
155-
156133
void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
157134
const MCSubtargetInfo &STI,
158135
raw_ostream &O) {
@@ -165,13 +142,6 @@ void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
165142
O << formatHex(MI->getOperand(OpNo).getImm());
166143
}
167144

168-
void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
169-
const MCSubtargetInfo &STI,
170-
raw_ostream &O) {
171-
O << " offset:";
172-
printSMEMOffset(MI, OpNo, STI, O);
173-
}
174-
175145
void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
176146
const MCSubtargetInfo &STI,
177147
raw_ostream &O) {
@@ -698,26 +668,6 @@ void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
698668
O << " blgp:" << Imm;
699669
}
700670

701-
void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
702-
const MCSubtargetInfo &STI,
703-
raw_ostream &O) {
704-
unsigned Imm = MI->getOperand(OpNo).getImm();
705-
if (!Imm)
706-
return;
707-
708-
O << " cbsz:" << Imm;
709-
}
710-
711-
void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
712-
const MCSubtargetInfo &STI,
713-
raw_ostream &O) {
714-
unsigned Imm = MI->getOperand(OpNo).getImm();
715-
if (!Imm)
716-
return;
717-
718-
O << " abid:" << Imm;
719-
}
720-
721671
void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
722672
const MCSubtargetInfo &STI,
723673
raw_ostream &O) {
@@ -731,34 +681,6 @@ void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
731681
O << ", ";
732682
}
733683

734-
void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo,
735-
const MCSubtargetInfo &STI,
736-
raw_ostream &O) {
737-
O << " wait_vdst:";
738-
printU4ImmDecOperand(MI, OpNo, O);
739-
}
740-
741-
void AMDGPUInstPrinter::printWaitVAVDst(const MCInst *MI, unsigned OpNo,
742-
const MCSubtargetInfo &STI,
743-
raw_ostream &O) {
744-
O << " wait_va_vdst:";
745-
printU4ImmDecOperand(MI, OpNo, O);
746-
}
747-
748-
void AMDGPUInstPrinter::printWaitVMVSrc(const MCInst *MI, unsigned OpNo,
749-
const MCSubtargetInfo &STI,
750-
raw_ostream &O) {
751-
O << " wait_vm_vsrc:";
752-
printU4ImmDecOperand(MI, OpNo, O);
753-
}
754-
755-
void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo,
756-
const MCSubtargetInfo &STI,
757-
raw_ostream &O) {
758-
O << " wait_exp:";
759-
printU4ImmDecOperand(MI, OpNo, O);
760-
}
761-
762684
bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
763685
unsigned OpNo) const {
764686
return OpNo == 0 && (Desc.TSFlags & SIInstrFlags::DPP) &&
@@ -1155,29 +1077,6 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
11551077
}
11561078
}
11571079

1158-
void AMDGPUInstPrinter::printDppRowMask(const MCInst *MI, unsigned OpNo,
1159-
const MCSubtargetInfo &STI,
1160-
raw_ostream &O) {
1161-
O << " row_mask:";
1162-
printU4ImmOperand(MI, OpNo, STI, O);
1163-
}
1164-
1165-
void AMDGPUInstPrinter::printDppBankMask(const MCInst *MI, unsigned OpNo,
1166-
const MCSubtargetInfo &STI,
1167-
raw_ostream &O) {
1168-
O << " bank_mask:";
1169-
printU4ImmOperand(MI, OpNo, STI, O);
1170-
}
1171-
1172-
void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
1173-
const MCSubtargetInfo &STI,
1174-
raw_ostream &O) {
1175-
unsigned Imm = MI->getOperand(OpNo).getImm();
1176-
if (Imm) {
1177-
O << " bound_ctrl:1";
1178-
}
1179-
}
1180-
11811080
void AMDGPUInstPrinter::printDppFI(const MCInst *MI, unsigned OpNo,
11821081
const MCSubtargetInfo &STI, raw_ostream &O) {
11831082
using namespace llvm::AMDGPU::DPP;
@@ -1812,14 +1711,18 @@ void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
18121711
O << ' ' << formatDec(Imm);
18131712
}
18141713

1815-
void AMDGPUInstPrinter::printByteSel(const MCInst *MI, unsigned OpNo,
1816-
const MCSubtargetInfo &STI,
1817-
raw_ostream &O) {
1818-
uint8_t Imm = MI->getOperand(OpNo).getImm();
1819-
if (!Imm)
1820-
return;
1821-
1822-
O << " byte_sel:" << formatDec(Imm);
1714+
void AMDGPUInstPrinter::printNamedInt(const MCInst *MI, unsigned OpNo,
1715+
const MCSubtargetInfo &STI,
1716+
raw_ostream &O, StringRef Prefix,
1717+
unsigned Width, bool PrintInHex,
1718+
bool AlwaysPrint) {
1719+
int64_t V = MI->getOperand(OpNo).getImm();
1720+
if (AlwaysPrint || V != 0) {
1721+
if (Width)
1722+
V &= maxUIntN(Width);
1723+
1724+
O << ' ' << Prefix << ':' << (PrintInHex ? formatHex(V) : formatDec(V));
1725+
}
18231726
}
18241727

18251728
#include "AMDGPUGenAsmWriter.inc"

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

Lines changed: 4 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,6 @@ class AMDGPUInstPrinter : public MCInstPrinter {
4141
void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
4242
const MCSubtargetInfo &STI, raw_ostream &O);
4343
void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44-
void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4544
void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4645
void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
4746
const MCSubtargetInfo &STI, raw_ostream &O);
@@ -52,16 +51,10 @@ class AMDGPUInstPrinter : public MCInstPrinter {
5251
void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
5352
raw_ostream &O);
5453

55-
void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
56-
raw_ostream &O);
57-
void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
58-
raw_ostream &O);
5954
void printSMRDOffset8(const MCInst *MI, unsigned OpNo,
6055
const MCSubtargetInfo &STI, raw_ostream &O);
6156
void printSMEMOffset(const MCInst *MI, unsigned OpNo,
6257
const MCSubtargetInfo &STI, raw_ostream &O);
63-
void printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
64-
const MCSubtargetInfo &STI, raw_ostream &O);
6558
void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
6659
const MCSubtargetInfo &STI, raw_ostream &O);
6760
void printCPol(const MCInst *MI, unsigned OpNo,
@@ -114,12 +107,6 @@ class AMDGPUInstPrinter : public MCInstPrinter {
114107
raw_ostream &O);
115108
void printDPPCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
116109
raw_ostream &O);
117-
void printDppRowMask(const MCInst *MI, unsigned OpNo,
118-
const MCSubtargetInfo &STI, raw_ostream &O);
119-
void printDppBankMask(const MCInst *MI, unsigned OpNo,
120-
const MCSubtargetInfo &STI, raw_ostream &O);
121-
void printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
122-
const MCSubtargetInfo &STI, raw_ostream &O);
123110
void printDppFI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
124111
raw_ostream &O);
125112
void printSDWASel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
@@ -158,21 +145,9 @@ class AMDGPUInstPrinter : public MCInstPrinter {
158145
const MCSubtargetInfo &STI, raw_ostream &O);
159146
void printBLGP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
160147
raw_ostream &O);
161-
void printCBSZ(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
162-
raw_ostream &O);
163-
void printABID(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
164-
raw_ostream &O);
165148
bool needsImpliedVcc(const MCInstrDesc &Desc, unsigned OpNo) const;
166149
void printDefaultVccOperand(bool FirstOperand, const MCSubtargetInfo &STI,
167150
raw_ostream &O);
168-
void printWaitVDST(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
169-
raw_ostream &O);
170-
void printWaitEXP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
171-
raw_ostream &O);
172-
void printWaitVAVDst(const MCInst *MI, unsigned OpNo,
173-
const MCSubtargetInfo &STI, raw_ostream &O);
174-
void printWaitVMVSrc(const MCInst *MI, unsigned OpNo,
175-
const MCSubtargetInfo &STI, raw_ostream &O);
176151

177152
void printExpSrcN(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
178153
raw_ostream &O, unsigned N);
@@ -186,8 +161,10 @@ class AMDGPUInstPrinter : public MCInstPrinter {
186161
const MCSubtargetInfo &STI, raw_ostream &O);
187162
void printExpTgt(const MCInst *MI, unsigned OpNo,
188163
const MCSubtargetInfo &STI, raw_ostream &O);
189-
void printByteSel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
190-
raw_ostream &O);
164+
void printNamedInt(const MCInst *MI, unsigned OpNo,
165+
const MCSubtargetInfo &STI, raw_ostream &O,
166+
StringRef Prefix, unsigned Width, bool PrintInHex,
167+
bool AlwaysPrint);
191168

192169
public:
193170
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 20 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1015,18 +1015,30 @@ def SDWAVopcDst : BoolRC {
10151015
let PrintMethod = "printVOPDst";
10161016
}
10171017

1018-
class NamedIntOperand<ValueType Type, string Prefix, bit Optional = 1,
1018+
class NamedIntOperand<ValueType Type, string prefix, bit Optional = 1,
10191019
string name = NAME>
10201020
: CustomOperand<Type, Optional, name> {
1021+
string Prefix = prefix;
1022+
10211023
let PredicateMethod =
10221024
"getPredicate([](const AMDGPUOperand &Op) -> bool { "#
10231025
"return Op.isImmTy(AMDGPUOperand::"#ImmTy#"); })";
1026+
10241027
string Validator = "[](int64_t V) { return true; }";
10251028
string ConvertMethod = "[](int64_t &V) { return "#Validator#"(V); }";
10261029
let ParserMethod =
10271030
"[this](OperandVector &Operands) -> ParseStatus { "#
10281031
"return parseIntWithPrefix(\""#Prefix#"\", Operands, "#
10291032
"AMDGPUOperand::"#ImmTy#", "#ConvertMethod#"); }";
1033+
1034+
bit PrintInHex = 0;
1035+
bit AlwaysPrint = 0;
1036+
int Width = 0;
1037+
let PrintMethod = "[this](const MCInst *MI, unsigned OpNo, "
1038+
"const MCSubtargetInfo &STI, raw_ostream &O) { "
1039+
"printNamedInt(MI, OpNo, STI, O, \""#Prefix#"\", "#
1040+
Width#", "#!if(PrintInHex, "true", "false")#", "#
1041+
!if(AlwaysPrint, "true", "false")#"); }";
10301042
}
10311043

10321044
class NamedBitOperand<string Id, string Name = NAME>
@@ -1065,6 +1077,7 @@ class ArrayOperand0<string Id, string Name = NAME>
10651077

10661078
let ImmTy = "ImmTyOffset" in
10671079
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
1080+
let PrintMethod = "printOffset" in
10681081
def Offset : NamedIntOperand<i32, "offset">;
10691082
let Validator = "isUInt<8>" in {
10701083
def Offset0 : NamedIntOperand<i8, "offset0">;
@@ -1103,6 +1116,7 @@ def exp_vm : NamedBitOperand<"vm", "ExpVM">;
11031116

11041117
def FORMAT : CustomOperand<i8>;
11051118

1119+
let PrintMethod = "printDMask" in
11061120
def DMask : NamedIntOperand<i16, "dmask">;
11071121

11081122
def Dim : CustomOperand<i8, /*optional=*/1>;
@@ -1123,16 +1137,17 @@ def IndexKey8bit : CustomOperand<i32, 1>;
11231137
def dpp8 : CustomOperand<i32, 0, "DPP8">;
11241138
def dpp_ctrl : CustomOperand<i32, 0, "DPPCtrl">;
11251139

1126-
let DefaultValue = "0xf" in {
1140+
let DefaultValue = "0xf", PrintInHex = 1, AlwaysPrint = 1, Width = 4 in {
11271141
def DppRowMask : NamedIntOperand<i32, "row_mask">;
11281142
def DppBankMask : NamedIntOperand<i32, "bank_mask">;
11291143
}
11301144
def DppBoundCtrl : NamedIntOperand<i1, "bound_ctrl"> {
11311145
let ConvertMethod = "[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }";
11321146
}
11331147

1134-
let DecoderMethod = "decodeDpp8FI" in
1148+
let DecoderMethod = "decodeDpp8FI", PrintMethod = "printDppFI" in
11351149
def Dpp8FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
1150+
let PrintMethod = "printDppFI" in
11361151
def Dpp16FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
11371152

11381153
def blgp : CustomOperand<i32, 1, "BLGP">;
@@ -1146,6 +1161,7 @@ def hwreg : CustomOperand<i32, 0, "Hwreg">;
11461161

11471162
def exp_tgt : CustomOperand<i32, 0, "ExpTgt">;
11481163

1164+
let AlwaysPrint = 1 in {
11491165
def WaitVDST : NamedIntOperand<i8, "wait_vdst"> {
11501166
let Validator = "isUInt<4>";
11511167
}
@@ -1158,6 +1174,7 @@ def WaitVAVDst : NamedIntOperand<i8, "wait_va_vdst"> {
11581174
def WaitVMVSrc : NamedIntOperand<i8, "wait_vm_vsrc"> {
11591175
let Validator = "isUInt<1>";
11601176
}
1177+
} // End AlwaysPrint = 1
11611178

11621179
def ByteSel : NamedIntOperand<i8, "byte_sel"> {
11631180
let Validator = "isUInt<2>";

‎llvm/lib/Target/AMDGPU/SMInstructions.td

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,10 @@ def smrd_offset_8 : ImmOperand<i32, "SMRDOffset8", 1>;
1111
let EncoderMethod = "getSMEMOffsetEncoding",
1212
DecoderMethod = "decodeSMEMOffset" in {
1313
def SMEMOffset : ImmOperand<i32, "SMEMOffset", 1>;
14-
def SMEMOffsetMod : NamedIntOperand<i32, "offset", 0>;
14+
def SMEMOffsetMod : NamedIntOperand<i32, "offset", 0> {
15+
let AlwaysPrint = 1;
16+
let PrintInHex = 1;
17+
}
1518
def OptSMEMOffsetMod : NamedIntOperand<i32, "offset"> {
1619
let ImmTy = SMEMOffsetMod.ImmTy;
1720
let PredicateMethod = SMEMOffsetMod.PredicateMethod;

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