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LiqinWengLiqinWeng
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[LV][VPlan] set FastMathFlags on EVLRecipe
Currently support: 1. vp.fpext/vp.fptrunc of VPWidenCastRecipe 2. vp.select of VPWidenSelectRecipe 3. vp.select of VPInstruction
1 parent df41557 commit 6d7d92f

11 files changed

+43
-31
lines changed

‎llvm/lib/Transforms/Vectorize/VPlan.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1002,10 +1002,10 @@ void VPlan::execute(VPTransformState *State) {
10021002
setName("Final VPlan");
10031003
LLVM_DEBUG(dump());
10041004

1005-
// LLVM_DEBUG(dbgs() << "Executing best plan with VF=" << State->VF
1006-
// << ", UF=" << getUF() << '\n');
1007-
// setName("Final VPlan");
1008-
// LLVM_DEBUG(dump());
1005+
LLVM_DEBUG(dbgs() << "Executing best plan with VF=" << State->VF
1006+
<< ", UF=" << getUF() << '\n');
1007+
setName("Final VPlan");
1008+
LLVM_DEBUG(dump());
10091009

10101010
// Disconnect the middle block from its single successor (the scalar loop
10111011
// header) in both the CFG and DT. The branch will be recreated during VPlan

‎llvm/lib/Transforms/Vectorize/VPlan.h

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1652,8 +1652,8 @@ class VPWidenIntrinsicRecipe : public VPRecipeWithIRFlags {
16521652

16531653
VPWidenIntrinsicRecipe(Intrinsic::ID VectorIntrinsicID,
16541654
ArrayRef<VPValue *> CallArguments, Type *Ty,
1655-
DebugLoc DL = {})
1656-
: VPRecipeWithIRFlags(VPDef::VPWidenIntrinsicSC, CallArguments),
1655+
FastMathFlags FMFs, DebugLoc DL = {})
1656+
: VPRecipeWithIRFlags(VPDef::VPWidenIntrinsicSC, CallArguments, FMFs),
16571657
VectorIntrinsicID(VectorIntrinsicID), ResultTy(Ty) {
16581658
LLVMContext &Ctx = Ty->getContext();
16591659
AttributeList Attrs = Intrinsic::getAttributes(Ctx, VectorIntrinsicID);
@@ -1667,9 +1667,10 @@ class VPWidenIntrinsicRecipe : public VPRecipeWithIRFlags {
16671667

16681668
VPWidenIntrinsicRecipe(Intrinsic::ID VectorIntrinsicID,
16691669
std::initializer_list<VPValue *> CallArguments,
1670-
Type *Ty, DebugLoc DL = {})
1670+
Type *Ty, FastMathFlags FMFs, DebugLoc DL = {})
16711671
: VPWidenIntrinsicRecipe(VectorIntrinsicID,
1672-
ArrayRef<VPValue *>(CallArguments), Ty, DL) {}
1672+
ArrayRef<VPValue *>(CallArguments), Ty, FMFs,
1673+
DL) {}
16731674

16741675
~VPWidenIntrinsicRecipe() override = default;
16751676

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -991,8 +991,11 @@ void VPWidenIntrinsicRecipe::execute(VPTransformState &State) {
991991
CI->getOperandBundlesAsDefs(OpBundles);
992992

993993
CallInst *V = State.Builder.CreateCall(VectorF, Args, OpBundles);
994-
995-
setFlags(V);
994+
// vector-predication intrinsics only accept FMF flags, while vector intrinsic
995+
// can support all flags.
996+
bool VPIntrinsic = VPIntrinsic::isVPIntrinsic(VectorIntrinsicID);
997+
if ((VPIntrinsic && isa<FPMathOperator>(V)) || !VPIntrinsic)
998+
setFlags(V);
996999

9971000
if (!V->getType()->isVoidTy())
9981001
State.set(this, V);

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1498,19 +1498,24 @@ static VPRecipeBase *createEVLRecipe(VPValue *HeaderMask,
14981498
assert(VPIntrinsic::getMaskParamPos(VPID) &&
14991499
VPIntrinsic::getVectorLengthParamPos(VPID) &&
15001500
"Expected VP intrinsic");
1501-
1501+
FastMathFlags FMFs = {};
1502+
if (CR->hasFastMathFlags())
1503+
FMFs = CR->getFastMathFlags();
15021504
SmallVector<VPValue *> Ops(CR->operands());
15031505
Ops.push_back(&AllOneMask);
15041506
Ops.push_back(&EVL);
1505-
return new VPWidenIntrinsicRecipe(
1506-
VPID, Ops, TypeInfo.inferScalarType(CR), CR->getDebugLoc());
1507+
return new VPWidenIntrinsicRecipe(VPID, Ops,
1508+
TypeInfo.inferScalarType(CR),
1509+
FMFs, CR->getDebugLoc());
15071510
})
15081511
.Case<VPWidenSelectRecipe>([&](VPWidenSelectRecipe *Sel) {
15091512
SmallVector<VPValue *> Ops(Sel->operands());
15101513
Ops.push_back(&EVL);
1514+
// TODO: getFlags from recipe instead of by underlying instruction
1515+
FastMathFlags FMFs = {};
15111516
return new VPWidenIntrinsicRecipe(Intrinsic::vp_select, Ops,
15121517
TypeInfo.inferScalarType(Sel),
1513-
Sel->getDebugLoc());
1518+
FMFs, Sel->getDebugLoc());
15141519
})
15151520
.Case<VPInstruction>([&](VPInstruction *VPI) -> VPRecipeBase * {
15161521
VPValue *LHS, *RHS;
@@ -1521,11 +1526,14 @@ static VPRecipeBase *createEVLRecipe(VPValue *HeaderMask,
15211526
if (!match(VPI, m_Select(m_Specific(HeaderMask), m_VPValue(LHS),
15221527
m_VPValue(RHS))))
15231528
return nullptr;
1529+
FastMathFlags FMFs = {};
1530+
if (VPI->hasFastMathFlags())
1531+
FMFs = VPI->getFastMathFlags();
15241532
// Use all true as the condition because this transformation is
15251533
// limited to selects whose condition is a header mask.
15261534
return new VPWidenIntrinsicRecipe(
15271535
Intrinsic::vp_merge, {&AllOneMask, LHS, RHS, &EVL},
1528-
TypeInfo.inferScalarType(LHS), VPI->getDebugLoc());
1536+
TypeInfo.inferScalarType(LHS), FMFs, VPI->getDebugLoc());
15291537
})
15301538
.Default([&](VPRecipeBase *R) { return nullptr; });
15311539
}

‎llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -662,7 +662,7 @@ define nofpclass(nan inf) float @vp_reduction_with_fastflags(ptr %a, ptr %b, i6
662662
; IF-EVL-OUTLOOP-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP12]], i32 0
663663
; IF-EVL-OUTLOOP-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP13]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
664664
; IF-EVL-OUTLOOP-NEXT: [[VP_OP:%.*]] = call fast <vscale x 4 x float> @llvm.vp.fadd.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> [[VEC_PHI]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
665-
; IF-EVL-OUTLOOP-NEXT: [[TMP14]] = call <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[VP_OP]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP10]])
665+
; IF-EVL-OUTLOOP-NEXT: [[TMP14]] = call fast <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[VP_OP]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP10]])
666666
; IF-EVL-OUTLOOP-NEXT: [[TMP15:%.*]] = zext i32 [[TMP10]] to i64
667667
; IF-EVL-OUTLOOP-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP15]], [[EVL_BASED_IV]]
668668
; IF-EVL-OUTLOOP-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]

‎llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -374,7 +374,7 @@ define void @vp_fpext_with_fastflags(ptr %a, ptr %b, i64 %N) {
374374
; IF-EVL-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP13]]
375375
; IF-EVL-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 0
376376
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x float> @llvm.vp.load.nxv2f32.p0(ptr align 4 [[TMP15]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]]), !alias.scope [[META30:![0-9]+]]
377-
; IF-EVL-NEXT: [[TMP16:%.*]] = call <vscale x 2 x double> @llvm.vp.fpext.nxv2f64.nxv2f32(<vscale x 2 x float> [[VP_OP_LOAD]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]])
377+
; IF-EVL-NEXT: [[TMP16:%.*]] = call fast <vscale x 2 x double> @llvm.vp.fpext.nxv2f64.nxv2f32(<vscale x 2 x float> [[VP_OP_LOAD]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]])
378378
; IF-EVL-NEXT: [[TMP17:%.*]] = getelementptr inbounds double, ptr [[A]], i64 [[TMP13]]
379379
; IF-EVL-NEXT: [[TMP18:%.*]] = getelementptr inbounds double, ptr [[TMP17]], i32 0
380380
; IF-EVL-NEXT: call void @llvm.vp.store.nxv2f64.p0(<vscale x 2 x double> [[TMP16]], ptr align 8 [[TMP18]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]]), !alias.scope [[META33:![0-9]+]], !noalias [[META30]]
@@ -540,7 +540,7 @@ define void @vp_fptrunc_with_fastflags(ptr %a, ptr %b, i64 %N) {
540540
; IF-EVL-NEXT: [[TMP14:%.*]] = getelementptr inbounds double, ptr [[B]], i64 [[TMP13]]
541541
; IF-EVL-NEXT: [[TMP15:%.*]] = getelementptr inbounds double, ptr [[TMP14]], i32 0
542542
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x double> @llvm.vp.load.nxv2f64.p0(ptr align 8 [[TMP15]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]]), !alias.scope [[META44:![0-9]+]]
543-
; IF-EVL-NEXT: [[TMP16:%.*]] = call <vscale x 2 x float> @llvm.vp.fptrunc.nxv2f32.nxv2f64(<vscale x 2 x double> [[VP_OP_LOAD]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]])
543+
; IF-EVL-NEXT: [[TMP16:%.*]] = call fast <vscale x 2 x float> @llvm.vp.fptrunc.nxv2f32.nxv2f64(<vscale x 2 x double> [[VP_OP_LOAD]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]])
544544
; IF-EVL-NEXT: [[TMP17:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP13]]
545545
; IF-EVL-NEXT: [[TMP18:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i32 0
546546
; IF-EVL-NEXT: call void @llvm.vp.store.nxv2f32.p0(<vscale x 2 x float> [[TMP16]], ptr align 4 [[TMP18]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]]), !alias.scope [[META47:![0-9]+]], !noalias [[META44]]

‎llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1108,7 +1108,7 @@ define float @fadd(ptr %a, i64 %n, float %start) {
11081108
; IF-EVL-NEXT: [[TMP13:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 0
11091109
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP13]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
11101110
; IF-EVL-NEXT: [[VP_OP:%.*]] = call reassoc <vscale x 4 x float> @llvm.vp.fadd.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> [[VEC_PHI]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
1111-
; IF-EVL-NEXT: [[TMP14]] = call <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[VP_OP]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP10]])
1111+
; IF-EVL-NEXT: [[TMP14]] = call reassoc <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[VP_OP]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP10]])
11121112
; IF-EVL-NEXT: [[TMP15:%.*]] = zext i32 [[TMP10]] to i64
11131113
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP15]], [[EVL_BASED_IV]]
11141114
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]
@@ -1311,7 +1311,7 @@ define float @fmin(ptr %a, i64 %n, float %start) #0 {
13111311
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP12]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])
13121312
; IF-EVL-NEXT: [[TMP13:%.*]] = fcmp fast olt <vscale x 4 x float> [[VP_OP_LOAD]], [[VEC_PHI]]
13131313
; IF-EVL-NEXT: [[TMP14:%.*]] = call <vscale x 4 x float> @llvm.vp.select.nxv4f32(<vscale x 4 x i1> [[TMP13]], <vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP9]])
1314-
; IF-EVL-NEXT: [[TMP15]] = call <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP9]])
1314+
; IF-EVL-NEXT: [[TMP15]] = call fast <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP9]])
13151315
; IF-EVL-NEXT: [[TMP16:%.*]] = zext i32 [[TMP9]] to i64
13161316
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]
13171317
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]
@@ -1438,7 +1438,7 @@ define float @fmax(ptr %a, i64 %n, float %start) #0 {
14381438
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP12]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])
14391439
; IF-EVL-NEXT: [[TMP13:%.*]] = fcmp fast ogt <vscale x 4 x float> [[VP_OP_LOAD]], [[VEC_PHI]]
14401440
; IF-EVL-NEXT: [[TMP14:%.*]] = call <vscale x 4 x float> @llvm.vp.select.nxv4f32(<vscale x 4 x i1> [[TMP13]], <vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP9]])
1441-
; IF-EVL-NEXT: [[TMP15]] = call <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP9]])
1441+
; IF-EVL-NEXT: [[TMP15]] = call fast <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP9]])
14421442
; IF-EVL-NEXT: [[TMP16:%.*]] = zext i32 [[TMP9]] to i64
14431443
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]
14441444
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]
@@ -1727,8 +1727,8 @@ define float @fmuladd(ptr %a, ptr %b, i64 %n, float %start) {
17271727
; IF-EVL-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr [[B:%.*]], i64 [[TMP11]]
17281728
; IF-EVL-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 0
17291729
; IF-EVL-NEXT: [[VP_OP_LOAD1:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP15]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
1730-
; IF-EVL-NEXT: [[TMP16:%.*]] = call <vscale x 4 x float> @llvm.vp.fmuladd.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> [[VP_OP_LOAD1]], <vscale x 4 x float> [[VEC_PHI]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
1731-
; IF-EVL-NEXT: [[TMP17]] = call <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[TMP16]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP10]])
1730+
; IF-EVL-NEXT: [[TMP16:%.*]] = call reassoc <vscale x 4 x float> @llvm.vp.fmuladd.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> [[VP_OP_LOAD1]], <vscale x 4 x float> [[VEC_PHI]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
1731+
; IF-EVL-NEXT: [[TMP17]] = call reassoc <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[TMP16]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP10]])
17321732
; IF-EVL-NEXT: [[TMP18:%.*]] = zext i32 [[TMP10]] to i64
17331733
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP18]], [[EVL_BASED_IV]]
17341734
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]

‎llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-select-intrinsics.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -156,9 +156,9 @@ define void @vp_select_with_fastflags(ptr %a, ptr %b, ptr %c, i64 %N) {
156156
; IF-EVL-NEXT: [[VP_OP_LOAD5:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP21]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])
157157
; IF-EVL-NEXT: [[TMP22:%.*]] = fcmp fast ogt <vscale x 4 x float> [[VP_OP_LOAD]], [[VP_OP_LOAD5]]
158158
; IF-EVL-NEXT: [[VP_OP:%.*]] = call fast <vscale x 4 x float> @llvm.vp.fadd.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> splat (float 1.000000e+01), <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])
159-
; IF-EVL-NEXT: [[TMP23:%.*]] = call <vscale x 4 x float> @llvm.vp.select.nxv4f32(<vscale x 4 x i1> [[TMP22]], <vscale x 4 x float> [[VP_OP]], <vscale x 4 x float> [[VP_OP_LOAD5]], i32 [[TMP16]])
160-
; IF-EVL-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[TMP17]]
161-
; IF-EVL-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw float, ptr [[TMP24]], i32 0
159+
; IF-EVL-NEXT: [[TMP23:%.*]] = call fast <vscale x 4 x float> @llvm.vp.select.nxv4f32(<vscale x 4 x i1> [[TMP22]], <vscale x 4 x float> [[VP_OP]], <vscale x 4 x float> [[VP_OP_LOAD5]], i32 [[TMP16]])
160+
; IF-EVL-NEXT: [[TMP24:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP17]]
161+
; IF-EVL-NEXT: [[TMP25:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i32 0
162162
; IF-EVL-NEXT: call void @llvm.vp.store.nxv4f32.p0(<vscale x 4 x float> [[TMP23]], ptr align 4 [[TMP25]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])
163163
; IF-EVL-NEXT: [[TMP26:%.*]] = zext i32 [[TMP16]] to i64
164164
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP26]], [[EVL_BASED_IV]]

‎llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -217,7 +217,7 @@ define void @vp_fpext_with_fastfalgs(ptr %a, ptr %b, i64 %N) {
217217
; IF-EVL-NEXT: CLONE ir<[[GEP1:%.+]]> = getelementptr inbounds ir<%b>, vp<[[ST]]>
218218
; IF-EVL-NEXT: vp<[[PTR1:%[0-9]+]]> = vector-pointer ir<[[GEP1]]>
219219
; IF-EVL-NEXT: WIDEN ir<[[LD1:%.+]]> = vp.load vp<[[PTR1]]>, vp<[[EVL]]>
220-
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[FPEXT:%.+]]> = call llvm.vp.fpext(ir<[[LD1]]>, ir<true>, vp<[[EVL]]>)
220+
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[FPEXT:%.+]]> = call reassoc nnan ninf nsz arcp contract afn llvm.vp.fpext(ir<[[LD1]]>, ir<true>, vp<[[EVL]]>)
221221
; IF-EVL-NEXT: CLONE ir<[[GEP2:%.+]]> = getelementptr inbounds ir<%a>, vp<[[ST]]>
222222
; IF-EVL-NEXT: vp<[[PTR2:%[0-9]+]]> = vector-pointer ir<[[GEP2]]>
223223
; IF-EVL-NEXT: WIDEN vp.store vp<[[PTR2]]>, vp<[[FPEXT]]>, vp<[[EVL]]>
@@ -313,7 +313,7 @@ define void @vp_fptrunc_with_fastflags(ptr %a, ptr %b, i64 %N) {
313313
; IF-EVL-NEXT: CLONE ir<[[GEP1:%.+]]> = getelementptr inbounds ir<%b>, vp<[[ST]]>
314314
; IF-EVL-NEXT: vp<[[PTR1:%[0-9]+]]> = vector-pointer ir<[[GEP1]]>
315315
; IF-EVL-NEXT: WIDEN ir<[[LD1:%.+]]> = vp.load vp<[[PTR1]]>, vp<[[EVL]]>
316-
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[FPTRUNC:%.+]]> = call llvm.vp.fptrunc(ir<[[LD1]]>, ir<true>, vp<[[EVL]]>)
316+
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[FPTRUNC:%.+]]> = call reassoc nnan ninf nsz arcp contract afn llvm.vp.fptrunc(ir<[[LD1]]>, ir<true>, vp<[[EVL]]>)
317317
; IF-EVL-NEXT: CLONE ir<[[GEP2:%.+]]> = getelementptr inbounds ir<%a>, vp<[[ST]]>
318318
; IF-EVL-NEXT: vp<[[PTR2:%[0-9]+]]> = vector-pointer ir<[[GEP2]]>
319319
; IF-EVL-NEXT: WIDEN vp.store vp<[[PTR2]]>, vp<[[FPTRUNC]]>, vp<[[EVL]]>

‎llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -245,7 +245,7 @@ define nofpclass(nan inf) float @vp_reduction_with_fastflags(ptr %a, ptr %b, i64
245245
; IF-EVL-OUTLOOP-NEXT: vp<[[PTR1:%[0-9]+]]> = vector-pointer ir<[[GEP1]]>
246246
; IF-EVL-OUTLOOP-NEXT: WIDEN ir<[[LD1:%.+]]> = vp.load vp<[[PTR1]]>, vp<[[EVL]]>
247247
; IF-EVL-OUTLOOP-NEXT: WIDEN ir<[[FADD:%.+]]> = vp.fadd reassoc nnan ninf nsz arcp contract afn ir<[[LD1]]>, ir<[[RDX_PHI]]>, vp<[[EVL]]>
248-
; IF-EVL-OUTLOOP-NEXT: WIDEN-INTRINSIC vp<[[RDX_SELECT]]> = call llvm.vp.merge(ir<true>, ir<[[FADD]]>, ir<[[RDX_PHI]]>, vp<[[EVL]]>)
248+
; IF-EVL-OUTLOOP-NEXT: WIDEN-INTRINSIC vp<[[RDX_SELECT]]> = call reassoc nnan ninf nsz arcp contract afn llvm.vp.merge(ir<true>, ir<[[FADD]]>, ir<[[RDX_PHI]]>, vp<[[EVL]]>)
249249
; IF-EVL-OUTLOOP-NEXT: SCALAR-CAST vp<[[CAST:%[0-9]+]]> = zext vp<[[EVL]]> to i64
250250
; IF-EVL-OUTLOOP-NEXT: EMIT vp<[[IV_NEXT]]> = add vp<[[CAST]]>, vp<[[EVL_PHI]]>
251251
; IF-EVL-OUTLOOP-NEXT: EMIT vp<[[IV_NEXT_EXIT:%.+]]> = add vp<[[IV]]>, vp<[[VFUF]]>

‎llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -117,8 +117,8 @@ define void @vp_select_with_fastflags(ptr %a, ptr %b, ptr %c, i64 %N) {
117117
; IF-EVL-NEXT: WIDEN ir<[[LD2:%.+]]> = vp.load vp<[[PTR2]]>, vp<[[EVL]]>
118118
; IF-EVL-NEXT: WIDEN ir<[[FCMP:%.+]]> = fcmp ogt ir<[[LD1]]>, ir<[[LD2]]>
119119
; IF-EVL-NEXT: WIDEN ir<[[FADD:%.+]]> = vp.fadd reassoc nnan ninf nsz arcp contract afn ir<[[LD1]]>, ir<1.000000e+01>, vp<[[EVL]]>
120-
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[SELECT:%.+]]> = call llvm.vp.select(ir<[[FCMP]]>, ir<[[FADD]]>, ir<[[LD2]]>, vp<[[EVL]]>)
121-
; IF-EVL-NEXT: CLONE ir<[[GEP3:%.+]]> = getelementptr inbounds nuw ir<%a>, vp<[[ST]]>
120+
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[SELECT:%.+]]> = call reassoc nnan ninf nsz arcp contract afn llvm.vp.select(ir<[[FCMP]]>, ir<[[FADD]]>, ir<[[LD2]]>, vp<[[EVL]]>)
121+
; IF-EVL-NEXT: CLONE ir<[[GEP3:%.+]]> = getelementptr inbounds ir<%a>, vp<[[ST]]>
122122
; IF-EVL-NEXT: vp<[[PTR3:%.+]]> = vector-pointer ir<[[GEP3]]>
123123
; IF-EVL-NEXT: WIDEN vp.store vp<[[PTR3]]>, vp<%7>, vp<[[EVL]]>
124124
; IF-EVL-NEXT: SCALAR-CAST vp<[[CAST:%.+]]> = zext vp<[[EVL]]> to i64

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